Part Verification and Datasheet Review

C

cherepanyadima

Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.

flux

I’ll inspect the part metadata, look for an official datasheet if needed, then compare the symbol/footprint/pins against the datasheet and update the Datasheet property if missing.

flux

The project already has an Analog Devices datasheet URL set, so I’m using that as the source of truth and moving into pin/footprint verification.
Created a project doc

MAX20303BEWN+T Part Review

View Document
Date: 2026-07-08 Project/part: MAX20303BEWN+T

flux

Completed the part review and saved the detailed findings in MAX20303BEWN+T Part Review.
  • Datasheet URL was already set to the official Analog Devices page, so no update was needed.
  • Symbol pin mapping and main 56-WLP footprint geometry match the datasheet.
  • Flagged issues: Part Type is too narrow, explicit package metadata is missing, footprint pad diameter should be reviewed against ADI AN1891/assembler rules, and there are minor text/naming cleanup items.
Fix metadata and footprint
Fix flagged issues
Review WLP pads
Run validation checks
Add package property
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Files

Pins

Symbol

Layout

3D View

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
DRN
A1
Output
Peripheral
right
23
ERM/LRA haptic driver negative output.
DRP
A2
Output
Peripheral
left
22
ERM/LRA haptic driver positive output.
HDGND
A3
Ground
Power
left
28
Haptic driver ground. Keep within -0.3V to +0.3V of GSUB.
SYS_1
A4
Power Out
Power
left
3
System load connection, SYS bump A4. Connect both SYS bumps together on PCB with low impedance; bypass common node with minimum 10µF to GND.
L2OUT
A5
Power Out
Power
right
4
LDO2 output. Bypass with 1µF capacitor to GND.
BK2GND
A6
Ground
Power
right
26
Buck2 ground. Keep within -0.3V to +0.3V of GSUB.
BK2LX
A7
Passive
Voltage Regulator
right
7
Buck2 regulator switch. Connect through 2.2µH inductor to BK2OUT.
SCL
B1
Input
Communication
left
13
I2C serial clock input.
SDA
B2
Bi-Directional
Communication
right
13
I2C serial data input/open-drain output.
CPP
B3
Passive
Voltage Regulator
left
12
Charge pump flying-capacitor positive terminal. Connect 22nF min, 33nF max capacitor to CPN.
CPN
B4
Passive
Voltage Regulator
right
12
Charge pump flying-capacitor negative terminal. Connect 22nF min, 33nF max capacitor to CPP.
CPOUT
B5
Power Out
Voltage Regulator
left
11
Charge pump output. Bypass with 1µF capacitor to GND.
L2IN
B6
Power In
Power
right
3
LDO2 input. Bypass with 1µF capacitor to GND.
BK2OUT
B7
Power Out
Voltage Regulator
right
6
Buck2 regulator output. Bypass with 10µF capacitor to GND.
LED2
C1
Output
Peripheral
left
24
Current sink output 2.
DGND
C2
Ground
Power
left
26
Digital ground. Keep within -0.3V to +0.3V of GSUB.
MPC4
C3
Bi-Directional
GPIO
right
19
Multipurpose control I/O 4.
MPC1
C4
Bi-Directional
GPIO
right
17
Multipurpose control I/O 1.
MPC0
C5
Bi-Directional
GPIO
left
17
Multipurpose control I/O 0.
CELL
C6
Input
Analog
left
19
Fuel-gauge voltage input. Bypass with 0.1µF capacitor to GND.
BBOUT
C7
Power Out
Voltage Regulator
right
9
Buck-boost regulator output. Bypass with 10µF capacitor to GND.
LED1
D1
Output
Peripheral
right
24
Current sink output 1.
PFN1
D2
Bi-Directional
Control
left
15
Configurable power-mode control pin, e.g. KIN.

MAX20303BEWN+T