Part Review and Datasheet Verification

flux

Completed the LMH0394SQE/NOPB review and documented the findings in LMH0394SQE/NOPB Part Review. The symbol pinout matches the datasheet for non-SPI/pin mode, the footprint pad count is consistent with 16 WQFN pins plus exposed DAP, and the main issues are unspecified pin types, ambiguous DAP naming, missing SPI alternate-function representation, and needing exact footprint geometry confirmation against TI RUM0016A.
Open items:
  • Add/confirm visible Datasheet URL property as https://www.ti.com/lit/ds/symlink/lmh0394.pdf if it is not already exposed.
  • Add per-pin descriptions/types and clarify pin 17 as exposed DAP/VEE.
  • Decide whether this part should model SPI-mode alternate pin functions.
Suggested next steps:
  1. Update pin descriptions and pin types from the datasheet.
  2. Rename/describe VEE_3 as DAP or VEE_DAP.
  3. Verify exact pad dimensions/pitch against the TI land pattern.
A

adrian95

Update the pin types/descriptions, clarify the DAP, then verify the footprint geometry.

flux

I’ll update the terminal pin metadata from the datasheet, rename/describe the exposed pad clearly as DAP/VEE, then inspect the footprint geometry against the TI RUM0016A land pattern.

flux

Pin metadata is updated; I noticed a few values used non-standard enums, so I’m normalizing those now before verification.

flux

Updated the pin types/descriptions and clarified pin 17 as the DAP/exposed thermal pad tied to VEE/GND. I also verified the footprint: pad count, body outline, 0.65 mm pitch, and pin-1 marker match RUM0016A, but the land sizes differ from TI’s example layout: current perimeter pads are 0.35 × 0.85 mm vs TI example 0.3 × 0.6 mm, and exposed pad is 2.7 mm vs TI example 2.6 mm.
Open items:
  • Decide whether to keep the current solderability-oriented footprint or revise it to TI’s example land pattern.
  • Optionally rename VEE_3 to DAP or VEE_DAP for visual clarity.
Suggested next steps:
  1. Revise the footprint pad geometry to TI’s example land pattern.
  2. Rename the DAP terminal for clarity.
  3. Add an SPI-mode symbol variant if this part should support both pin-mode and SPI-mode labeling.
Fix footprint and DAP
Revise land pattern
Rename DAP terminal
Run DRC review
Add SPI variant
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Files

Pins

Symbol

Layout

3D View

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
VEE_1
1
Ground
Ground
VEE negative power supply / ground
SDI
2
Input
Analog
Serial data true input; analog high-speed SDI input
~SDI
3
Input
Analog
Serial data complement input; analog high-speed SDI input
SPI_EN
4
Input
Control Bus
LVCMOS SPI register access enable; internal pulldown; high = SPI mode, low = pin mode
AEC+
5
Bi-Directional
Analog
AEC loop filter external capacitor positive connection; analog I/O; optional 1 uF capacitor
AEC-
6
Bi-Directional
Analog
AEC loop filter external capacitor negative connection; analog I/O; optional 1 uF capacitor
BYPASS
7
Input
Control Bus
LVCMOS equalization bypass in non-SPI mode; internal pulldown; high = bypassed, low = normal operation. Alternate SPI-mode function: CD output.
MUTEREF
8
Input
Reference
Analog mute reference input; sets carrier detect/mute threshold; may be unconnected or grounded for normal CD operation
VEE_2
9
Ground
Ground
VEE / ground in non-SPI mode; connect to ground or drive logic low. Alternate SPI-mode function: SS input.
~SDO
10
Output
Data Bus
Serial data complement output; internally terminated LVDS output
SDO
11
Output
Data Bus
Serial data true output; internally terminated LVDS output
AUTO_SLEEP
12
Input
Control Bus
LVCMOS auto sleep input in non-SPI mode; internal pullup; high = power down when no input detected, low = normal operation. Alternate SPI-mode function: MISO output.
VCC_1
13
Power In
Power
Positive 2.5 V power supply
MUTE
14
Input
Control Bus
LVCMOS output mute input in non-SPI mode; internal pulldown; high = outputs muted, low = outputs enabled. Alternate SPI-mode function: SCK input.
~CD
15
Output
Control Bus
Carrier detect LVCMOS output in non-SPI mode; datasheet CD is high when no input signal is detected and low when input signal is detected. Alternate SPI-mode function: MOSI input.
VCC_2
16
Power In
Power
Positive 2.5 V power supply
VEE_3
17
Ground
Ground
DAP exposed thermal pad; connect to VEE / ground for thermal, mechanical, and electrical performance

LMH0394SQE/NOPB