Part Review and Datasheet Verification

flux

Completed the LMH0394SQE/NOPB review and documented the findings in LMH0394SQE/NOPB Part Review. The symbol pinout matches the datasheet for non-SPI/pin mode, the footprint pad count is consistent with 16 WQFN pins plus exposed DAP, and the main issues are unspecified pin types, ambiguous DAP naming, missing SPI alternate-function representation, and needing exact footprint geometry confirmation against TI RUM0016A.
Open items:
  • Add/confirm visible Datasheet URL property as https://www.ti.com/lit/ds/symlink/lmh0394.pdf if it is not already exposed.
  • Add per-pin descriptions/types and clarify pin 17 as exposed DAP/VEE.
  • Decide whether this part should model SPI-mode alternate pin functions.
Suggested next steps:
  1. Update pin descriptions and pin types from the datasheet.
  2. Rename/describe VEE_3 as DAP or VEE_DAP.
  3. Verify exact pad dimensions/pitch against the TI land pattern.
A

adrian95

Update the pin types/descriptions, clarify the DAP, then verify the footprint geometry.

flux

I’ll update the terminal pin metadata from the datasheet, rename/describe the exposed pad clearly as DAP/VEE, then inspect the footprint geometry against the TI RUM0016A land pattern.

flux

Pin metadata is updated; I noticed a few values used non-standard enums, so I’m normalizing those now before verification.

flux

Updated the pin types/descriptions and clarified pin 17 as the DAP/exposed thermal pad tied to VEE/GND. I also verified the footprint: pad count, body outline, 0.65 mm pitch, and pin-1 marker match RUM0016A, but the land sizes differ from TI’s example layout: current perimeter pads are 0.35 × 0.85 mm vs TI example 0.3 × 0.6 mm, and exposed pad is 2.7 mm vs TI example 2.6 mm.
Open items:
  • Decide whether to keep the current solderability-oriented footprint or revise it to TI’s example land pattern.
  • Optionally rename VEE_3 to DAP or VEE_DAP for visual clarity.
Suggested next steps:
  1. Revise the footprint pad geometry to TI’s example land pattern.
  2. Rename the DAP terminal for clarity.
  3. Add an SPI-mode symbol variant if this part should support both pin-mode and SPI-mode labeling.
Fix footprint and DAP
Revise land pattern
Rename DAP terminal
Run DRC review
Add SPI variant
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3D View

LMH0394SQE/NOPB Part Review
Sources
Current Part Information Observed
  • Project/name: LMH0394SQE/NOPB
  • Description: 3G HD/SD SDI low-power extended-reach adaptive cable equalizer
  • Manufacturer part number: LMH0394SQE/NOPB
  • Manufacturer: Texas Instruments
  • Package: 16-WQFN, 4 mm × 4 mm, TI RUM0016A
  • Pads/terminals in project: 17, representing 16 package pins plus exposed DAP/thermal pad
Datasheet Key Specs
  • Device: LMH0394 3G HD/SD SDI low-power extended-reach adaptive cable equalizer
  • Package: WQFN (TI RUM), 16 pins plus exposed DAP/thermal pad
  • Body size: 4.0 mm × 4.0 mm nominal
  • Package height: 0.8 mm max
  • Pitch: 0.65 mm
  • Recommended PCB land pattern: 16 × 0.6 mm × 0.3 mm perimeter lands, 2.6 mm exposed thermal pad land, 0.2 mm typical thermal vias
  • Supply: single 2.5 V nominal, 2.375 V to 2.625 V operating range
  • Operating temperature: −40 °C to +85 °C
  • Input data rate: 125 Mbps to 2.97 Gbps
  • Typical normal power: 115 mW; typical supply current 45 mA, max 65 mA
  • Power-save current: 7 mA typ, 10 mA max
  • Input coupling capacitance: 1 µF
  • Input SDI trace target: 75 Ω ±5% single-ended
  • Output SDO trace target: 100 Ω ±5% differential
  • Logic thresholds: VIH min 1.7 V, VIL max 0.7 V
Pin Metadata Updates Completed
The symbol terminals now have datasheet-based Pin Type, Pin Description, and general Pin Group properties. Alternate SPI-mode functions are called out in the affected pin descriptions.

Table

PinSymbolUpdated TypeDescription Summary
1VEE_1GroundVEE negative supply / ground
2SDIInputSerial data true analog high-speed SDI input
3~SDIInputSerial data complement analog high-speed SDI input
4SPI_ENInputSPI register access enable; high = SPI mode, low = pin mode
5AEC+Bi-DirectionalAEC loop filter capacitor positive connection
6AEC-Bi-DirectionalAEC loop filter capacitor negative connection
7BYPASSInputEqualization bypass in non-SPI mode; alternate SPI function: CD
8MUTEREFInputAnalog mute reference input
9VEE_2GroundVEE/ground or logic low in non-SPI mode; alternate SPI function: SS
10~SDOOutputSerial data complement LVDS output
11SDOOutputSerial data true LVDS output
12AUTO_SLEEPInputAuto sleep input in non-SPI mode; alternate SPI function: MISO
13VCC_1Power InPositive 2.5 V supply
14MUTEInputOutput mute in non-SPI mode; alternate SPI function: SCK
15~CDOutputCarrier detect output; datasheet CD is high when no input is detected and low when input is detected; alternate SPI function: MOSI
16VCC_2Power InPositive 2.5 V supply
17VEE_3GroundDAP exposed thermal pad; connect to VEE/GND
DAP Clarification Completed
  • Pin 17 remains represented as VEE_3, but its metadata now explicitly states: DAP exposed thermal pad; connect to VEE / ground for thermal, mechanical, and electrical performance.
  • The pin group is Ground, and the terminal should be interpreted as the exposed thermal pad / DAP tied to VEE.
  • If visual clarity is desired, a future cleanup can rename the terminal from VEE_3 to DAP or VEE_DAP.
Footprint Geometry Verification
Datasheet / TI RUM0016A Reference
  • Package body: 4.0 mm × 4.0 mm nominal
  • Pitch: 0.65 mm
  • Package lead dimensions: 0.3 mm to 0.5 mm length, 0.25 mm to 0.35 mm width
  • Example board layout land pattern: 16 × 0.6 mm × 0.3 mm perimeter lands
  • Example exposed thermal pad land: 2.6 mm
  • Thermal via: 0.2 mm typical, optional/application-dependent
Current Footprint Observed
  • Footprint asset: QFN65P400X400X80-17N.kicad_mod
  • Footprint description: RUM0016A_2020
  • Perimeter pads: 16 pads present
  • Exposed pad: pad 17 present
  • Body/fab outline: ±2.0 mm, matching 4.0 mm × 4.0 mm body
  • Courtyard: ±2.625 mm, 5.25 mm × 5.25 mm
  • Pin pitch: 0.65 mm, from pad center spacing
  • Perimeter pad size: 0.35 mm × 0.85 mm
  • Exposed pad size: 2.7 mm × 2.7 mm
  • Pin-1 marking: present
  • 3D model: LMH0394SQE_NOPB.stp
Mismatches / Issues Flagged
  1. Pin metadata is now populated and aligned with the datasheet. No remaining missing Pin Type or Pin Description fields were observed after the update.
  2. DAP is clarified but not renamed. The exposed pad is still visibly named VEE_3; its description now makes the DAP function clear. Rename to DAP or VEE_DAP if the library convention allows terminal renaming.
  3. Footprint pad count, body outline, pitch, and pin-1 marker match the TI RUM0016A package concept. It has 16 perimeter pads plus one exposed pad.
  4. Footprint land dimensions differ from the TI example board layout. Current perimeter pads are 0.35 mm × 0.85 mm while the datasheet example board layout lists 0.3 mm × 0.6 mm lands. Current exposed pad is 2.7 mm × 2.7 mm while the datasheet example lists 2.6 mm. This may be a CAD-library solderability variant, but it should be reviewed before release/manufacturing.
  5. No thermal vias are present in the footprint. TI shows 0.2 mm typical vias in the example layout, but notes vias are application-dependent. This is not necessarily a footprint error, but the board layout should add/handle thermal vias if needed.
  • Decide whether to keep the current land pattern or revise perimeter pads to TI's example 0.6 mm × 0.3 mm and exposed pad to 2.6 mm.
  • Consider renaming VEE_3 to DAP / VEE_DAP for symbol clarity.
  • If this part must support SPI-mode usage cleanly, add alternate symbol text or create a SPI-mode variant symbol.

  • Sources

  • Current Part Information Observed

  • Datasheet Key Specs

  • Pin Metadata Updates Completed

  • DAP Clarification Completed

  • Footprint Geometry Verification

  • Datasheet / TI RUM0016A Reference

  • Current Footprint Observed

  • Mismatches / Issues Flagged

  • Recommended Next Actions