Part Datasheet Audit
Populate all pin types and descriptions from the datasheet.
Thought for 6 sec
I’ll update each terminal’s Pin Type and Pin Description from the LM5013-Q1 datasheet, then verify the properties were applied.
Worked for 56 sec
Pin properties are updated; I’m doing a final readback now to confirm every terminal matches the datasheet-derived mapping.
Thought for 23 sec
Updated and verified all LM5013-Q1 terminal Pin Type and Pin Description properties from the datasheet.
Open items:
- Used
Open Collectorfor PGOOD because Flux has no separateOpen Drainpin type option. - Used
Passivefor EP because the datasheet says the exposed pad has no internal electrical connection, though it should be tied to GND copper thermally.
Suggested next steps:
- Review/fix the exposed pad footprint size versus TI’s thermal land.
- Run a final part audit after footprint cleanup.
Fix EP and review
Adjust exposed pad
Run final audit
Check layout DRC
Update audit document
Refine this doc
Ask about this doc
Part Datasheet Audit: LM5013QDDARQ1
Date: 2026-07-15
Scope
Reviewed the current Flux part information for LM5013QDDARQ1 against the Texas Instruments LM5013-Q1 datasheet and TI product information. Checked metadata, schematic terminals, pin numbering/descriptions, and PCB footprint geometry.
Datasheet source
- Current project Datasheet URL was already populated:
https://storage.googleapis.com/graviton-electric-symbols/document_assets/user-uploaded/ff404494436941c5206c32318bac86ad2dba36405417f1ea65e8cead08d8b985.pdf - Official TI datasheet found during review:
https://www.ti.com/lit/ds/symlink/lm5013-q1.pdf - TI product/orderable page confirms
LM5013QDDARQ1is active, DDA / 8-pin SO PowerPAD / HSOIC package, -40°C to 150°C operating temperature.
Because a Datasheet URL was already set, no Datasheet URL property update was required by the request. The existing uploaded PDF content matches the TI datasheet content used for this review.
Current part information observed
Table
| Field | Current value | Datasheet / expected value | Status |
|---|---|---|---|
| Manufacturer Part Number | LM5013QDDARQ1 | LM5013QDDARQ1 | OK |
| Manufacturer Name | Texas Instruments | Texas Instruments | OK |
| Description | Switching Voltage Regulators 6-V to 100-V input, 3.5-A non-synchronous buck DC/DC converter with ultra-low quiescent current | Automotive 100-V input, 3.5-A non-synchronous buck DC/DC converter with ultra-low IQ | OK |
| Part Type | Linear Regulator | Switching buck regulator / DC-DC converter / power management IC | Mismatch |
| Package or Case Code | TO | SO PowerPAD (DDA), 8 pins, DDA0008B PowerPAD SOIC | Mismatch |
| Pads | 9 | 8 signal/package pins plus exposed pad | OK as CAD convention |
| BOM items | None | This is a part project, so no BOM item is expected | OK |
Key datasheet specs
- Device: LM5013-Q1 automotive buck regulator
- Orderable part number: LM5013QDDARQ1
- Manufacturer: Texas Instruments
- Topology: non-synchronous step-down buck regulator, constant on-time control
- Input voltage range: 6 V to 100 V recommended operating range
- Output current: 3.0 A to 3.5 A range per recommended operating conditions; marketed as 3.5 A max DC load current
- Integrated switch: 100-V, 0.25-ohm high-side MOSFET
- Switching frequency: programmable; recommended up to 1000 kHz
- Quiescent current examples from datasheet extraction:
- Shutdown current: 3.1 uA typical, 9.9 uA max
- Sleep current: 10 uA typical, 20 uA max
- Standby current: 25 uA typical, 40 uA max
- Active current: 450 uA typical
- Reference voltage: 1.2 V internal reference
- Soft-start: fixed 3.5 ms internal soft-start
- Temperature: -40°C to 150°C junction range
- Qualification/features: AEC-Q100, Functional Safety-Capable, CISPR 25 Class 5-oriented feature set
- Package: 8-pin SO PowerPAD DDA, DDA0008B, 1.7 mm max height
- MSL/reflow: Level-2-260C-1 YEAR per package addendum extraction
Schematic symbol / pinout cross-check
Table
| Pin / pad | Current terminal | Datasheet name | Datasheet type | Datasheet function | Status |
|---|---|---|---|---|---|
| 1 | GND | GND | G | Ground connection for internal circuits | OK |
| 2 | VIN | VIN | P/I | Regulator supply input to high-side MOSFET and internal bias regulator | OK |
| 3 | EN/UVLO | EN/UVLO | I | Precision enable and UVLO programming input | OK |
| 4 | RON | RON | I | On-time programming pin; resistor to GND sets buck switch on-time | OK |
| 5 | FB | FB | I | Feedback input of voltage regulation comparator | OK |
| 6 | PGOOD | PGOOD | O | Open-drain power-good indicator; requires 10 kΩ to 100 kΩ pullup | OK |
| 7 | BST | BST | P/I | Bootstrap gate-drive supply; requires 2.2 nF, 50 V X7R capacitor to SW | OK |
| 8 | SW | SW | P | Switching node connected to source of high-side NMOS buck switch | OK |
| 9 / EP | EP | EP | — | Exposed pad, no internal electrical connection; connect to GND and large copper for thermal resistance | OK as CAD pad numbering convention |
Schematic symbol findings
- Pin numbering and terminal names match the datasheet top-view pinout.
- The exposed pad is numbered as pad 9 in Flux while TI labels it EP without a numeric pin. This is a normal CAD convention if the footprint also numbers the exposed pad as 9.
- All terminal Pin Type values are currently
Unspecified; the datasheet provides explicit G/P/I/O categories. - Pin Description fields are not populated on the terminals. This should be improved using the datasheet functions above.
Footprint cross-check
Current footprint asset:
SOIC127P600X170-9N.kicad_modObserved footprint geometry from the embedded KiCad module:
- Signal pads 1-8: 0.65 mm × 1.525 mm
- Signal pad pitch: 1.27 mm
- Signal pad row positions: x = ±2.712 mm, giving 5.424 mm row span
- Exposed pad 9: 2.4 mm × 3.1 mm
- Fabrication body outline: 3.9 mm × 4.9 mm
- Courtyard: 7.45 mm × 5.5 mm
- 3D model present:
LM5013QDDARQ1.stp
TI DDA0008B land-pattern / package extraction:
- Package: DDA0008B PowerPAD SOIC, 1.7 mm max height
- Body: 4.8 to 5.0 mm length, 3.8 to 4.0 mm width
- Overall width: 5.8 to 6.2 mm typical
- Pitch: 1.27 mm
- Signal land pattern: 8 × 1.55 mm × 0.6 mm
- Distance across signal pads: 5.4 mm
- Exposed thermal pad package range: 2.11 to 2.71 mm × 2.8 to 3.4 mm
- Example board layout exposed pad / metal pad: 2.95 mm × 4.9 mm, with 2.71 mm × 3.4 mm solder mask opening
- Optional vias: 0.2 mm typical, 1.3 mm typical spacing; vias under paste should be filled, plugged, or tented.
Table
| Feature | Current footprint | TI datasheet / land pattern | Status |
|---|---|---|---|
| Signal pad count | 8 | 8 | OK |
| Exposed pad | Pad 9 | EP / exposed thermal pad | OK as CAD convention |
| Pitch | 1.27 mm | 1.27 mm | OK |
| Signal pad size | 0.65 mm × 1.525 mm | 0.6 mm × 1.55 mm | Acceptable small library variation |
| Signal row span | 5.424 mm | 5.4 mm | Acceptable small variation |
| Body outline | 3.9 mm × 4.9 mm | approx. 3.8-4.0 mm × 4.8-5.0 mm | OK |
| Package height implied by name | X170 | 1.7 mm max | OK |
| Exposed pad copper | 2.4 mm × 3.1 mm | TI example metal pad 2.95 mm × 4.9 mm; mask opening 2.71 mm × 3.4 mm | Potential mismatch / thermal concern |
| Thermal vias | None embedded in footprint | Optional in TI example depending on application | Note / possible improvement |
Mismatches and risks
-
Part Type is incorrect
- Current:
Linear Regulator - Expected: switching buck regulator / DC-DC converter / power management IC.
- Risk: misleading categorization for search, validation, and design guidance.
- Current:
-
Package or Case Code is incorrect
- Current:
TO - Expected:
DDA,SO PowerPAD,PowerPAD SOIC-8, orDDA0008B. - Risk: misleading procurement/mechanical classification.
- Current:
-
Pin types are unspecified
- Current: every terminal has
Pin Type: Unspecified. - Expected: GND = Ground; VIN/BST/SW = power-related; EN/UVLO/RON/FB = Input; PGOOD = open-drain Output; EP = thermal pad/passive/no internal electrical connection.
- Risk: weaker ERC behavior and poor part documentation.
- Current: every terminal has
-
Pin descriptions are missing
- Datasheet descriptions should be copied into the terminal Pin Description fields.
- Risk: users cannot understand required external connections directly from the symbol.
-
Exposed pad footprint may be thermally undersized relative to TI example board layout
- Current EP copper is 2.4 mm × 3.1 mm.
- TI example metal pad is 2.95 mm × 4.9 mm, though package pad and mask-opening dimensions are smaller.
- Risk: possible degraded thermal performance for a 3.5-A buck regulator unless the user adds adequate GND copper and thermal vias in the application PCB.
Recommended fixes
- Change part category from
Linear Regulatorto a switching-regulator/power-management category. - Change package metadata from
TOtoDDA/DDA0008B/SO PowerPAD-8. - Populate terminal Pin Type and Pin Description values from the datasheet.
- Review the exposed pad land pattern. If the goal is to follow TI's example layout, enlarge the EP metal pad toward 2.95 mm × 4.9 mm and consider thermal vias. If keeping the smaller pad, document it as an intentional reduced thermal land and require application-board copper/vias.
- Optionally update the Datasheet URL to the official TI URL even though the current uploaded PDF is already set and appears to be the same datasheet.
Overall verdict
The part is functionally close: MPN, manufacturer, description, pin names, pin numbering, and signal pad geometry are correct or acceptable. It is not yet production-quality because metadata is misleading, pin types/descriptions are missing, and the exposed-pad footprint should be reviewed for thermal compliance with the TI DDA land pattern.
Scope
Datasheet source
Current part information observed
Key datasheet specs
Schematic symbol / pinout cross-check
Schematic symbol findings
Footprint cross-check
Mismatches and risks
Recommended fixes
Overall verdict
