• AEC-Q100 qualified; ISO 26262 compliant and ASIL-D systems ready.
• Integrated boost regulator: 9 V, 300 mA, 2 MHz.
• Integrated buck pre-regulator: 6.5 V / 7.2 V, 1 A, 465 kHz.
• Integrated VCC5 LDO: 5 V, 250 mA.
• Configurable VCC LDO: 3.3 V / 5 V, 100 mA.
• Programmable external-FET VCORE buck: 0.8 V to 5 V, up to 1 A for L9396B.
• Normal battery operating range: 4.5 V to 19 V with boost (6 V required for start-up); 6 V to 19 V without boost.
• Ambient operating temperature: -40 °C to 135 °C.
• Junction temperature range: -40 °C to 175 °C; storage: -55 °C to 150 °C.
• Typical junction-to-ambient thermal resistance: 26 °C/W under the datasheet JEDEC 2s2p natural-convection condition; junction-to-case on the exposed-pad side: 2.9 °C/W.
• Package: TQFP64EP, 10 × 10 × 1 mm nominal body, 12 × 12 mm basic lead span, 0.50 mm pitch, 4.5 × 4.5 mm exposed die pad (Option A).

• Pins 1–64: every project pin number and pin name matches the datasheet pin table exactly.
• Pin descriptions: absent on every project terminal; all 64 datasheet descriptions are therefore missing.
• Pin types: every project terminal is set to Unspecified; all 64 conflict with the datasheet's Input, Output, I/O, or Supply classification.
• Local/Global classification: not represented in the current Flux terminal properties.
• Duplicated supplies/grounds: there are no duplicate pin numbers. Distinct ground domains are correctly named GNDA (14), GNDBST (52), and GNDD (54). NU (53) is a separate pin that the datasheet requires to be connected to ground voltage.
• Project terminal 65 / EP: the project adds a numbered schematic terminal named EP and PCB pad 65. The official pin table ends at pin 64 and does not define an electrical pin number, name, pin type, or required net for the exposed die pad. The package drawing does verify a 4.5 × 4.5 mm exposed pad. Treating it as a routable terminal may be useful, but its number and electrical connection are not verified by the datasheet and must not be assumed to be GNDA, GNDD, or GNDBST.

• Footprint asset: F_QFP50P1200X1200X120-65N.kicad_mod.
• Footprint description: TQFP64 (10x10x1 mm exp. pad down).
• 64 perimeter SMD pads numbered 1 through 64, plus center pad 65.
• Perimeter pad pitch is 0.50 mm on all four sides.
• Perimeter pad copper size is 0.30 × 1.475 mm.
• Pad-row centerline is 5.738 mm from package center.
• Center pad 65 is 4.50 × 4.50 mm.
• Fabrication outline is 10.00 × 10.00 mm with a pin-1 chamfer.
• Silkscreen has corner segments and a distinct pin-1 circular marker.
• The footprint includes a STEP model asset named L9396B.stp.
• No PCB rulesets are defined in the part project.

1. Project Part Type is Inductors. This is categorically wrong for the L9396B automotive power-management/System Basis IC and can corrupt search, BOM classification, and automated review. The accompanying Part Sub-Type: Fixed and present-but-empty Inductance property are consistent with, and add evidence of, the same erroneous inductor classification.
2. EP is authored as electrical terminal/pad number 65, but the official pin table contains only pins 1–64 and does not specify an exposed-pad electrical net. The physical exposed pad is real and correctly sized, but its electrical numbering and connection are unsupported by the datasheet. Do not assume a ground domain without additional official ST package/application guidance.

3. All 64 documented terminals have Pin Type: Unspecified. Each conflicts with the datasheet Input/Output/I/O/Supply classification, weakening ERC and semantic checks.
4. All 64 documented terminals are missing Pin Description. The names are correct, but the symbol omits the complete datasheet function text.
5. Package metadata is absent at project level. The footprint is consistent with TQFP64EP, but Package or Case Code is not populated.
6. NU pin 53 grounding requirement is not captured in its project description/type metadata. Its name and number match, but the datasheet explicitly says it must be connected to ground voltage.

7. No explicit footprint courtyard is visible. This is not a datasheet mismatch because the datasheet gives no recommended land pattern, but it may affect downstream placement checks.
8. The EP uses one full-size paste aperture. The datasheet does not specify paste-windowing, so correctness cannot be established from the primary source.
9. The STEP model is attached but cannot be dimensionally verified with the current inspection output. Its mere presence does not prove package height, seating, orientation, or pad alignment.

• The official datasheet provides a package mechanical drawing but no recommended PCB land pattern, solder-mask expansion, paste-window pattern, courtyard, or thermal-via layout. Those footprint details are therefore not verifiable against this primary document.
• The datasheet confirms an exposed pad and its 4.5 × 4.5 mm size but does not list it in the electrical pin table or state its required net in the extracted text. Its project terminal number/type/net are unverified.
• The scene tree exposes the STEP asset name but not a trustworthy measured bounding box; 3D geometry was not proven.
• Flux layout scene-tree numeric geometry is stored/rendered through mixed internal units; the authoritative footprint comparison used the embedded KiCad footprint payload and the rendered 10 mm fabrication outline rather than interpreting the raw computed decimals as millimeters.
• The Flux datasheet query result did not return immutable inline citation IDs. No fabricated citation markers were inserted. Re-run citation verification when the tool exposes markdown_inline/citation-map output.

• Datasheet URL: no mutation; it was already set to the direct official ST PDF.
• Symbol, terminal metadata, and footprint: intentionally not modified, per audit scope.
• Project file: created this Part Datasheet Audit record.