Part Datasheet Review


I couldn’t perform the part review or update the Datasheet property because no ACUs are currently available, so AI project inspection and editing are unavailable.
Remaining work:
  • Inspect MPN, package, 33-pin count, description, and properties.
  • Locate and set the official datasheet URL if absent.
  • Cross-check all five symbol sections, pin numbers/names/types, footprint pads, and pin descriptions.
  • Summarize electrical/mechanical specs and flag mismatches.
Check this schematic component against the datasheet for [MPN] and assign the correct pin orientation, section, and terminal order without changing, replacing, renumbering, or remapping any pins. Remove the Pin Group property from all pins if it exists. Place Power pins first and Ground pins last. Within each section, distribute the pins as evenly as possible between the left and right sides; for example, split 10 pins as 5/5 and 11 pins as 5/6 or 6/5. If a section contains only one pin, leave it on the most appropriate side. Keep the symbol compact, balanced, and visually symmetrical. If a pin function is unclear, assign Unclear / Check datasheet, then apply all changes directly to the schematic component.
I’ll identify the component and official datasheet, audit every existing pin without altering its mapping, then apply section, orientation, terminal-order, and Pin Group cleanup directly to the symbol.
Updated all 33 terminals against the official ESP32-S3 PowerFeather V2 datasheet.
  • Sections ordered: Power → Control → Analog IO → Digital IO → Ground
  • Balanced orientations: 2/2, 2/2, 3/3, 8/9, and 1/1
  • Assigned unique terminal order within every section
  • Removed Pin Group from every terminal
  • Added datasheet-backed pin descriptions
  • Verified pin names, numbers, types, and mappings were not changed or remapped
No unresolved pin functions or mapping mismatches were found.
Review pinout visually
Audit datasheet property
Create bring-up plan
Review footprint mapping

Name
Pin #
Type
Section
Pin Group
Orientation
Order
Sub-symbol
Pin Description
~RST
1
Input
2 Control
Left
1
Active-low ESP32-S3 module reset input
3V3
2
Power Out
1 Power
Right
3
Regulated 3.3 V header output
QON
3
Input
2 Control
Left
2
Ship-mode exit input
GND
4
Power In
5 Ground
Left
1
Ground return
A0
5
Bi-Directional
3 Analog IO
Left
1
Analog-capable Feather header GPIO A0
A1
6
Bi-Directional
3 Analog IO
Left
2
Analog-capable Feather header GPIO A1
A2
7
Bi-Directional
3 Analog IO
Left
3
Analog-capable Feather header GPIO A2
A3
8
Bi-Directional
3 Analog IO
Right
4
Analog-capable Feather header GPIO A3
A4
9
Bi-Directional
3 Analog IO
Right
5
Analog-capable Feather header GPIO A4
A5
10
Bi-Directional
3 Analog IO
Right
6
Analog-capable Feather header GPIO A5
SCK
11
Bi-Directional
4 Digital IO
Left
1
SPI clock / digital GPIO
MOSI
12
Bi-Directional
4 Digital IO
Left
2
SPI controller-out peripheral-in / digital GPIO
MISO
13
Bi-Directional
4 Digital IO
Right
9
SPI controller-in peripheral-out / digital GPIO
RX_D0
14
Bi-Directional
4 Digital IO
Right
10
UART RX alias / Feather D0 digital GPIO
TX_D1
15
Bi-Directional
4 Digital IO
Left
3
UART TX alias / Feather D1 digital GPIO
TX0_D2
16
Bi-Directional
4 Digital IO
Left
4
UART0 TX alias / Feather D2 digital GPIO
SDA
17
Bi-Directional
4 Digital IO
Left
5
I2C data / digital GPIO
SCL
18
Bi-Directional
4 Digital IO
Right
11
I2C clock / digital GPIO
D5
19
Bi-Directional
4 Digital IO
Left
6
Feather D5 digital GPIO
D6
20
Bi-Directional
4 Digital IO
Right
12
Feather D6 digital GPIO
D9
21
Bi-Directional
4 Digital IO
Left
7
Feather D9 digital GPIO
D10
22
Bi-Directional
4 Digital IO
Right
13
Feather D10 digital GPIO
D11
23
Bi-Directional
4 Digital IO
Left
8
Feather D11 digital GPIO

ESP32-S3 PowerFeather V2