I’m reading the complete symbol and PCB land pattern now, including all 57 terminals and stored properties.

Audit complete and the root Datasheet URL now points to the official Espressif document. All 57 pin numbers/names and the main footprint dimensions match; key issues are missing pin types/descriptions/groups, incorrect QFN56 terminology instead of LGA-7×7-57, missing explicit package metadata, and incorrect generic classification as Logic / AND.

Key N8R2 specs: dual-core LX7 up to 240 MHz, Wi‑Fi/BLE 5 LE, 8 MB Quad-SPI flash, 2 MB Quad-SPI PSRAM, 3.0–3.6 V, and −40°C to +85°C. Paste/mask implementation and 3D-model alignment could not be conclusively verified.

I’ll assign each of the 57 pins to exactly one broad functional group based on its primary datasheet function, keep Section equal to Pin Group, and verify there are no duplicates or omissions.

The grouping pass took longer than expected; I’m checking the persisted terminal properties before deciding whether any focused cleanup is needed.

Grouped all 57 pins into exclusive functional sections: Power, Ground, RF, Enable, GPIO, Low-Frequency Clock, Memory Interface, JTAG, UART, and No Connect. Each physical pin appears exactly once, with matching Section/Pin Group, ordered pins, consistent orientations, electrical types, and datasheet-based descriptions.