Part Datasheet Audit

Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.

Thought for 11 sec

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I’ll audit the part metadata, locate and attach the official datasheet if needed, then verify the symbol, footprint, and pin definitions against it and report any discrepancies.

Worked for 4 mins 35 sec

Created a project doc

DS1100Z-50+ Part Audit

View Document

Existing Datasheet property: https://datasheets.maximintegrated.com/en/ds/DS1100.pdf Current official Analog Devices URL: https://www.analog...

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Audit complete. The existing datasheet URL is valid, so no property update was needed; package geometry is broadly correct, but all eight symbol-to-pin assignments are incorrect, and pin types/descriptions are missing. Full specifications and the exact mismatch table are in DS1100Z-50+ Part Audit.

Fix mapping and review

Fix pin mapping

Add pin metadata

Set Part Type

Run validation

Files

Pins

Symbol

Layout

3D View

DS1100Z-50+ Part Audit

Datasheet

Existing Datasheet property: https://datasheets.maximintegrated.com/en/ds/DS1100.pdf
Current official Analog Devices URL: https://www.analog.com/media/en/technical-documentation/data-sheets/DS1100.pdf
The property was already populated, so it was not changed.
Manufacturer attribution: DS1100Z-50+ is an Analog Devices / Maxim Integrated device, not Mini-Circuits.

Metadata review

Table

Field	Project value	Result
MPN	DS1100Z-50+	Confirmed
Manufacturer	Analog Devices	Confirmed; legacy datasheet is Maxim-branded
Package	8-SOIC	Broadly correct but imprecise; official package is 8-lead SO, 150 mil narrow, code S8+4, outline 21-0041
Pin count	8	Confirmed
Description	Five-tap 50 ns delay line, 10 ns increments, 4.75–5.25 V, −40°C to +85°C, TTL/CMOS, ten 74LS loads/tap	Confirmed
Part Type	Missing	Metadata omission / review warning

The + suffix denotes lead-free/RoHS packaging.

Pinout cross-check

All eight project terminal numbers are mapped to the wrong functions compared with the official datasheet.

Table

Physical pin	Official function	Current project function	Result
1	VCC	IN	Mismatch
2	TAP 1 output	TAP_2	Mismatch
3	TAP 3 output	TAP_4	Mismatch
4	TAP 5 output	GND	Mismatch
5	GND	TAP_5	Mismatch
6	TAP 4 output	TAP_3	Mismatch
7	TAP 2 output	TAP_1	Mismatch
8	IN	VCC	Mismatch

Additional symbol issues:

Every terminal has Pin Type = Unspecified.
Expected types are: IN = input; TAP1–TAP5 = outputs; VCC = power input; GND = ground/power input.
Pin descriptions are absent.
Section, Pin Group, Pin Orientation, and Terminal Order are not defined.

Footprint review

Footprint asset: SOIC127P600X175-8N.kicad_mod
8 rectangular SMD pads, numbered 1–8
1.27 mm pitch
Pad size approximately 0.65 × 1.525 mm
Fabrication body approximately 3.90 × 4.90 mm
Pin-1 marking present
Geometry is consistent with a standard 8-lead 150 mil narrow SOIC and broadly matches ADI outline 21-0041 / land pattern 90-0096.

The footprint geometry and pad count are suitable, but the logical terminal-to-pad mapping inherits the incorrect pin assignments above. No symbol or footprint edits were made during this audit.

3D model

A dedicated DS1100Z-50+.stp model is assigned at origin, 0° rotation, 1:1 scale. Detailed mechanical conformity could not be confirmed from the structured model metadata, so exact body and lead alignment remains uncertain.

Key specifications

Function: five-tap fixed silicon delay line
Supply: 4.75–5.25 V, nominal 5 V
Operating temperature: −40°C to +85°C
Nominal tap delays: 10, 20, 30, 40, and 50 ns
Delay tolerance for ≤40 ns taps: ±2 ns at 25°C, ±3 ns over 0–70°C, ±4 ns over −40–85°C
Delay tolerance for >40 ns taps: ±5%, ±8%, and ±13% over those respective ranges
Logic thresholds: VIH ≥ 2.2 V; VIL ≤ 0.8 V
Output capability: IOH −1 mA at VOH = 4 V; IOL 12 mA at VOL = 0.5 V; up to ten 74LS loads per tap
Active supply current at 1 MHz: 30–50 mA with outputs open
Input leakage: ±1 µA
Input capacitance: 5 pF typical, 10 pF maximum
Power-up time: 200 µs maximum
Minimum input pulse width for the 50 ns version: nominally 10 ns
Absolute pin voltage: −0.5 V to +6.0 V
Datasheet notes that decoupling and PCB layout affect delay accuracy near maximum frequency.

Conclusion

The MPN, manufacturer, pin count, functional description, and general SOIC-8 footprint geometry are credible. The critical defect is the complete reversal/misassignment of all eight terminal functions to physical pin numbers; using the part as currently mapped would connect every signal and supply to the wrong package lead. The missing Part Type, unspecified electrical pin types, and absent pin descriptions are secondary metadata/symbol-quality issues.

Datasheet
Metadata review
Pinout cross-check
Footprint review
3D model
Key specifications
Conclusion