DRV2901 Part Review
https://www.ti.com/lit/ds/symlink/drv2901.pdf.DRV2901DDVR, and the footprint appears to be missing the exposed PowerPAD thermal pad.DRV2901DDVR if this part should be BOM-ready.Table
| Field | Current value / observation |
|---|---|
| Project / part name | DRV2901DDV |
| Description | Piezo-Electric Actuator Controller PMIC 44-HTSSOP |
| Manufacturer name | Texas Instruments |
| Manufacturer Part Number | DRV2901DDV |
| Datasheet URL | https://www.ti.com/lit/ds/symlink/drv2901.pdf |
| Part type | Integrated Circuit |
| Designator prefix | U |
| Symbol style | parametric-v1 |
| Schematic terminals | 44 Terminal entries |
| PCB signal pads found | 44 pads |
| Net count | 0, as expected for a standalone published part |
Table
| Item | Datasheet / TI value |
|---|---|
| Device | DRV2901 |
| Official orderable MPN found | DRV2901DDVR |
| Status | Active / production |
| Description | Single-channel PWM-input piezo transducer driver for ultrasonic cleaning with wide supply voltage |
| Package | HTSSOP (DDV), 44 pins, PowerPAD |
| Package size listed in datasheet | 14.0 mm x 8.1 mm |
| Package option addendum | HTSSOP (DDV) | 44, large tape-and-reel, 2000 qty |
| Operating temperature | 0°C to 125°C |
| RoHS | Yes |
| MSL / peak reflow | Level-3-260C-168 HR |
| Part marking | DRV2901 |
Table
| Spec | Value |
|---|---|
| Headline supply operation | 12 V to 48 V |
| PVDD_X recommended operating range | 0 V min, 50 V typ, 52.5 V max |
| GVDD_X recommended range | 10.8 V to 13.2 V, 12 V typ |
| VDD recommended range | 10.8 V to 13.2 V, 12 V typ |
| Peak power | Up to 50 W peak |
| Output MOSFET RDS(on) | 90 mΩ typ high-side and low-side at TJ = 25°C, GVDD = 12 V |
| PWM frequency | 20 kHz to 600 kHz |
| Minimum output-filter inductance | 5 µH min, 10 µH typ |
| VREG | 2.95 V min, 3.3 V typ, 3.65 V max |
| VDD supply current | 10 mA typ operating, 6 mA typ reset mode |
| Gate supply current per half-bridge | 8 mA typ at 50% duty, 0.3 mA typ reset mode |
| Half-bridge idle current | 15 mA typ at 50% duty without output filter/load; 500 µA typ reset/no switching |
| Logic input thresholds | VIH = 2 V, VIL = 0.8 V |
| SD / OTW sink current abs max | 9 mA |
| OTW threshold | 115°C min, 125°C typ, 135°C max |
| Overtemperature error | 145°C min, 155°C typ, 165°C max |
| Overcurrent response time | 250 ns typ |
| OC programming resistor range | 22 kΩ to 69 kΩ, 5% tolerance |
Table
| Parameter | Rating |
|---|---|
| VDD to AGND | -0.3 V to 13.2 V |
| GVDD_X to AGND | -0.3 V to 13.2 V |
| PVDD_X to GND_X | -0.3 V to 71 V |
| OUT_X to GND_X | -0.3 V to 71 V |
| BST_X to GND_X | -0.3 V to 79.7 V |
| VREG to AGND | -0.3 V to 4.2 V |
| PWM_X, OC_ADJ, M1, M2, M3 to AGND | -0.3 V to 4.2 V |
| RESET_X, SD, OTW to AGND | -0.3 V to 7 V |
| Maximum operating junction temperature | 0°C to 125°C |
| Storage temperature | -40°C to 125°C |
Table
| Pin / group | Datasheet requirement or note |
|---|---|
| BST_A / BST_B | External 0.1 µF capacitor to OUT_A / OUT_B required |
| GVDD_A / GVDD_B | 0.1 µF capacitor to AGND required |
| PVDD_A / PVDD_B | Close decoupling required: 0.01 µF in parallel with 1.0 µF to GND_A / GND_B |
| VDD | 47 µF in parallel with 0.1 µF to GND required |
| VREG | 0.1 µF capacitor to AGND required |
| OC_ADJ | Resistor to ground required for analog overcurrent programming |
| OTW | Open-drain, active-low overtemperature warning |
| SD | Open-drain, active-low shutdown signal |
| RESET | Active-low reset for half-bridges A and B |
| NC pins | Do not connect |
_N in the Flux symbol while TI omits the suffix and states active-low behavior in the descriptions.Table
| Pin | Flux terminal | Datasheet pin | Result |
|---|---|---|---|
| 1 | GVDD_A | GVDD_A | Match |
| 2 | OTW_N | OTW | Functional match; naming convention differs |
| 3 | NC | NC | Match |
| 4 | NC | NC | Match |
| 5 | SD_N | SD | Functional match; naming convention differs |
| 6 | GND | GND | Match |
| 7 | RESET_N | RESET | Functional match; naming convention differs |
| 8 | PWM_A | PWM_A | Match |
| 9 | OC_ADJ | OC_ADJ | Match |
| 10 | GND | GND | Match |
| 11 | AGND | AGND | Match |
| 12 | VREG | VREG | Match |
| 13 | VREG | VREG | Match |
| 14 | GND | GND | Match |
| 15 | VREG | VREG | Match |
| 16 | PWM_B | PWM_B | Match |
| 17 | RESET_N | RESET | Functional match; naming convention differs |
| 18 | GND | GND | Match |
| 19 | NC | NC | Match |
| 20 | NC | NC | Match |
| 21 | VDD | VDD | Match |
| 22 | GVDD_B | GVDD_B | Match |
| 23 | GVDD_B | GVDD_B | Match |
| 24 | NC | NC | Match |
| 25 | NC | NC | Match |
| 26 | NC | NC | Match |
| 27 | NC | NC | Match |
| 28 | GND | GND | Match |
| 29 | GND | GND | Match |
| 30 | GND_B | GND_B | Match |
| 31 | OUT_B | OUT_B | Match |
| 32 | PVDD_B | PVDD_B | Match |
| 33 | BST_B | BST_B | Match |
| 34 | BST_A | BST_A | Match |
| 35 | PVDD_A | PVDD_A | Match |
| 36 | OUT_A | OUT_A | Match |
| 37 | GND_A | GND_A | Match |
| 38 | GND | GND | Match |
| 39 | GND | GND | Match |
| 40 | NC | NC | Match |
| 41 | NC | NC | Match |
| 42 | NC | NC | Match |
| 43 | NC | NC | Match |
| 44 | GVDD_A | GVDD_A | Match |
Table
| Feature | Observed in Flux footprint | Datasheet / TI package info | Result |
|---|---|---|---|
| Signal pad count | 44 pads | 44 leads / signal lands | Match |
| Pin pitch | ~0.635 mm inferred from pad spacing | 0.635 mm | Match |
| Row spacing | ~7.45 mm inferred from pad centers | TI example board layout references ~7.5 mm signal row spacing | Close / likely acceptable |
| Signal pad size | ~1.955 mm x 0.392 mm inferred from tool values | TI package drawing example land size: 1.45 mm x 0.40 mm | Possible mismatch; may be IPC-derived but should be checked |
| Footprint label | DDV0044A-IPC_A | Current TI package drawing found as DDV0044D PowerPAD TSSOP | Revision/package-drawing mismatch risk |
| Exposed thermal pad | No separate thermal / PowerPAD pad node found | Package is 44-pin HTSSOP PowerPAD with exposed pad approx. 6.72–7.30 mm x 3.85–4.43 mm | Significant mismatch / production risk |
Pin Type = Unspecified, and no terminal-level pin descriptions are populated. The datasheet provides clear pin types: power, input, output/open-drain, output, and NC. This reduces ERC quality and usability.OTW_N, SD_N, and RESET_N; TI labels these pins OTW, SD, and RESET and describes active-low behavior. This is not a functional pinout error, but it is a datasheet naming mismatch.DRV2901DDV, while TI’s active orderable part number is DRV2901DDVR. DDV is the package code; R indicates tape-and-reel. For sourcing/BOM use, prefer DRV2901DDVR or add it as the orderable part number.DDV0044A-IPC_A, while the current TI package drawing located for the DDV PowerPAD TSSOP-44 is DDV0044D. This does not automatically prove incompatibility, but the land pattern should be verified against TI’s current package drawing before production.Scope
Current Flux Part Metadata
Official Datasheet / Vendor Information
Key Electrical Specs
Important Absolute Maximum Ratings
Datasheet-Required External Components / Pin Notes
Symbol Pinout Cross-Check
Footprint Cross-Check
Flagged Mismatches and Risks
Overall Conclusion