Part Audit Review

Fix the metadata, terminal names/types/descriptions, and exposed-pad footprint per the TI datasheet.
I’ll apply the TI-backed metadata, fully define all 65 terminals, correct the PowerPAD geometry, then re-inspect the symbol and footprint against PAP0064F.
Metadata and all terminals are updated; I’m doing the final readback of pin mapping, rendered symbol, and the corrected 6.5 × 8.0 mm PowerPAD.
Updated the part to TI’s BQ79616PAPRQ1 data: official datasheet, PAP0064F package metadata, and all 65 terminals now have correct names, electrical types, descriptions, grouping, and pin numbers. The centered PowerPAD is corrected to 6.5 × 8.0 mm, with reduced paste coverage.
  • Open item: Paste is a reduced single 3.5 × 5.0 mm aperture; segmented stencil apertures require rebuilding/augmenting the footprint geometry.
  • Verification confirms 65 unique terminals, 65 mapped pads, and no reported part-review findings.
Fix stencil paste
Review part quality
Create 3D package
REFHM
Pin Number
36
BBP
Pin Number
64
VC4
Pin Number
27
COMHP
Pin Number
43
VC12
Pin Number
11
GPIO2
Pin Number
60
CB16
Pin Number
2
AVSS
Pin Number
39
GPIO5
Pin Number
57
CB14
Pin Number
6
CB11
Pin Number
12
VC13
Pin Number
9
TSREF
Pin Number
51
CB13
Pin Number
8
VC3
Pin Number
29
COMLP
Pin Number
40
GPIO3
Pin Number
59
BAT
Pin Number
1
TX
Pin Number
53
CB7
Pin Number
20
CB10
Pin Number
14
CVSS
Pin Number
46
COMLN
Pin Number
41
CB6
Pin Number
22
COMHN
Pin Number
42
VC8
Pin Number
19
BBN
Pin Number
63
DVDD
Pin Number
49
VC0
Pin Number
35
VC11
Pin Number
13
CVDD
Pin Number
45
NEG5V
Pin Number
44
VC14
Pin Number
7
CB0
Pin Number
34
REFHP
Pin Number
37
GPIO8
Pin Number
54
GPIO6
Pin Number
56
CB8
Pin Number
18
VC6
Pin Number
23
POWERPAD
Pin Number
65
GPIO7
Pin Number
55
VC9
Pin Number
17
CB1
Pin Number
32
AVDD
Pin Number
38
VC15
Pin Number
5
NPNB
Pin Number
48
CB3
Pin Number
28
VC10
Pin Number
15
RX
Pin Number
52
CB15
Pin Number
4
GPIO1
Pin Number
61
CB5
Pin Number
24
DVSS
Pin Number
50
GPIO4
Pin Number
58
CB2
Pin Number
30
CB12
Pin Number
10
NFAULT
Pin Number
62
VC1
Pin Number
33
CB4
Pin Number
26
LDOIN
Pin Number
47
VC16
Pin Number
3
VC7
Pin Number
21
VC2
Pin Number
31
VC5
Pin Number
25
CB9
Pin Number
16

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Part Audit Report
Scope
Audit of project metadata, schematic symbol terminals, and PCB footprint against Texas Instruments BQ7961x-Q1 datasheet Rev. F (June 2026) and PAP0064F package information.
Authoritative references
The project already has a Datasheet URL populated, so it was not overwritten. The attached PDF identifies itself as the official TI datasheet, Rev. F.
Current metadata

Table


FieldCurrent valueAudit
Project/part namePBQ79616PAPTQ1Mismatch / questionable MPN
Manufacturer Part NumberPBQ79616PAPTQ1Mismatch: leading P is not part of the TI device MPN. Current TI orderable addendum lists BQ79616PAPRQ1; BQ79616PAPTQ1 appears in TI support discussions but is not in the current orderable table.
ManufacturerTexas InstrumentsCorrect
DescriptionBQ7961x-Q1 family, 12S/14S/16S automotive battery monitor/balancer/protectorFunctionally correct, but SafeTITM-26262 is malformed wording. Datasheet states functional-safety compliance and systematic/hardware capability up to ASIL D.
Package or Case CodeTOIncorrect. Correct package is PAP, 64-pin HTQFP / PowerPAD TQFP.
MountHardwareIncorrect/invalid classification; package is surface mount.
Part TypeIntegrated CircuitsBroad but not wrong; a more useful classification is battery monitor/balancer or power-management IC.
Designator PrefixICAcceptable, though U is the more common schematic convention.
Datasheet URLExisting uploaded PDFPresent and official-content; no update required by the request.
Datasheet key specifications
  • 16-series-cell automotive precision battery monitor, balancer, and integrated hardware protector.
  • Supports 6S to 16S operation for BQ79616-Q1.
  • Total module operating voltage: 9 V to 80 V; 11 V to 80 V for OTP programming.
  • Cell measurement range: generally -1 V to 5 V differential; VC1-to-VC0 is 0 V to 5 V.
  • ADC headline accuracy: ±1.5 mV typical condition stated in features; detailed guaranteed limits vary with voltage and temperature.
  • All cell channels measured within 128 µs.
  • Internal passive balancing, up to 240 mA stated in features, with thermal pause/resume management.
  • Eight GPIOs configurable for NTC/ADC, digital I/O, and SPI master functions.
  • UART plus isolated differential daisy-chain interfaces with optional ring architecture.
  • AEC-Q100 Grade 1: -40 °C to +125 °C ambient.
  • Functional-safety systematic and hardware capability up to ASIL D.
  • Package: PAP0064F, 64-pin HTQFP PowerPAD, 10 mm × 10 mm body, 0.5 mm pitch, 1.2 mm maximum height, plus exposed PowerPAD shown as pad 65.
Schematic symbol audit
Critical mismatch
The symbol contains 65 terminals, but every terminal is named only by its number (1 through 65). All terminal types are Unspecified, and no pin descriptions, functional groups, or electrical roles are present.
This makes the part unsafe to use because designers cannot distinguish cell-sense, balancing, supply, ground, communication, UART, GPIO, fault, and thermal-reference pins.
Required pin-name mapping

Table


PinDatasheet nameFunction/type summary
1BATPower input / top-of-module measurement
2CB16Cell-balance I/O
3VC16Cell-voltage input
4CB15Cell-balance I/O
5VC15Cell-voltage input
6CB14Cell-balance I/O
7VC14Cell-voltage input
8CB13Cell-balance I/O
9VC13Cell-voltage input
10CB12Cell-balance I/O
11VC12Cell-voltage input
12CB11Cell-balance I/O
13VC11Cell-voltage input
14CB10Cell-balance I/O
15VC10Cell-voltage input
16CB9Cell-balance I/O
17VC9Cell-voltage input
18CB8Cell-balance I/O
19VC8Cell-voltage input
20CB7Cell-balance I/O
21VC7Cell-voltage input
22CB6Cell-balance I/O
23VC6Cell-voltage input
24CB5Cell-balance I/O
25VC5Cell-voltage input
26CB4Cell-balance I/O
27VC4Cell-voltage input
28CB3Cell-balance I/O
29VC3Cell-voltage input
30CB2Cell-balance I/O
31VC2Cell-voltage input
32CB1Cell-balance I/O
33VC1Cell-voltage input
34CB0Cell-balance I/O
35VC0Cell-voltage input
36REFHMPrecision-reference ground
37REFHPPrecision-reference output
38AVDD5 V regulated analog output
39AVSSAnalog ground
40COMLPDaisy-chain differential I/O
41COMLNDaisy-chain differential I/O
42COMHNDaisy-chain differential I/O
43COMHPDaisy-chain differential I/O
44NEG5VNegative charge-pump supply pin
45CVDD5 V communications/I/O supply output
46CVSSCommunications ground
47LDOIN6 V preregulated analog input/sense
48NPNBExternal NPN base drive
49DVDD1.8 V regulated digital output
50DVSSDigital ground
51TSREF5 V thermistor reference/bias output
52RXUART receiver input
53TXUART transmitter output
54GPIO8Configurable analog/digital I/O
55GPIO7Configurable analog/digital I/O
56GPIO6Configurable analog/digital I/O
57GPIO5Configurable analog/digital I/O
58GPIO4Configurable analog/digital I/O
59GPIO3Configurable analog/digital I/O
60GPIO2Configurable analog/digital I/O
61GPIO1Configurable analog/digital I/O
62NFAULTActive-low fault output
63BBNBus-bar differential input negative
64BBPBus-bar differential input positive
65PowerPADExposed thermal pad; datasheet does not assign a signal name in the functional pin table
The physical pin count is therefore consistent only if the exposed PowerPAD is counted as pad 65. The datasheet markets the package as 64-pin HTQFP.
Footprint audit
Matching items
  • 64 perimeter signal pads plus one exposed center pad are present.
  • Perimeter pitch is 0.5 mm.
  • Signal-pad copper is approximately 0.30 mm × 1.475 mm, effectively matching the 0.30 mm × 1.50 mm example land pattern.
  • Overall signal-pad span is approximately 11.476 mm, close to the datasheet example's nominal 11.4 mm.
  • Pin numbering proceeds consistently around the four sides, and pad 65 is centered.
Mismatches / risks
  • Center pad 65 is 8 mm × 8 mm. TI's package drawing shows the physical exposed pad around 6.5 mm × 5.3 mm, while the example PCB land pattern uses a non-square exposed-pad land (reported as 6.5 mm × 8 mm). The current 8 mm × 8 mm copper land is oversized in at least one axis and should be corrected from the authoritative PAP0064F drawing.
  • No thermal-via pattern is present. TI marks vias as application-dependent/optional, so absence is not automatically wrong, but thermal and assembly requirements should be reviewed.
  • No solder-paste segmentation was visible in the inspected footprint. A full 8 mm × 8 mm paste opening would create excessive solder and float risk; TI provides stencil-opening guidance. Paste and solder-mask layers should be explicitly verified.
  • Package metadata says TO, which conflicts with the actual HTQFP geometry even though the perimeter pad arrangement resembles PAP0064F.
Overall disposition
Not ready for library use. The perimeter footprint is broadly close, but the metadata is incorrect, the PowerPAD geometry needs correction/verification, and the symbol has no functional pin names, electrical types, or descriptions. The symbol problem alone is a critical usability and connection-risk defect.
  1. Correct the MPN after confirming whether the intended procurement form is current BQ79616PAPRQ1 or a tray variant BQ79616PAPTQ1; remove the erroneous leading P in all cases.
  2. Set package to PAP0064F / HTQFP-64 PowerPAD, 10 mm × 10 mm, 0.5 mm pitch and mount to SMD.
  3. Rename and type all 65 symbol terminals using the pin table above; add datasheet-derived pin descriptions.
  4. Correct exposed-pad copper and verify solder-mask/paste geometry directly against PAP0064F.
  5. Keep the official TI datasheet URL available as a stable reference: https://www.ti.com/lit/ds/symlink/bq79616-q1.pdf
  • Scope

  • Authoritative references

  • Current metadata

  • Datasheet key specifications

  • Schematic symbol audit

  • Critical mismatch

  • Required pin-name mapping

  • Footprint audit

  • Matching items

  • Mismatches / risks

  • Overall disposition

  • Recommended corrections

Documents

Assets

PBQ79616PAPTQ1

PBQ79616PAPTQ1

PBQ79616PAPTQ1.stp3D Model
BQ79616-Q1-thumb.png

BQ79616-Q1-thumb.png

BQ79616-Q1-thumbThumbnail

PBQ79616PAPTQ1

QFP50P1200X1200X120-65N.kicad_modFootprint

PBQ79616PAPTQ1

PBQ79616PAPTQ1 Symbol.svgDefault

BQ79616-Q1

BQ79616-Q1 thumbnail
16-S automotive precision battery monitor, balancer and integrated protector with ASIL-D compliance
Battery monitor, balancer, and hardware protector designed to measure and monitor 6S to 16S battery modules in automotive battery management systems. The BQ79616-Q1 provides ±1.5 mV ADC accuracy, measures all cell channels within 128 µs, supports internal cell balancing up to 240 mA, and provides isolated differential daisy-chain communication with UART/SPI host interface support. It is housed in a 64-pin HTQFP package measuring 10 mm × 10 mm. #TexasInstruments #BQ79616Q1 #BatteryMonitor #BMS #BatteryManagement

Properties

BQ79616PAPRQ1

Battery Monitor / Balancer

Texas Instruments

Integrated Circuit

U

Surface Mount

parametric-v1

PAP0064F (HTQFP-64 PowerPAD, 10 mm x 10 mm, 0.5 mm pitch)

Pricing & Availability

DPN

Stock

Qty 1

3

0–32K

$7.5314–$8.398

3

0

$0.00

2

0

$0.00

1

15

$15.33

Controls