The render shows label congestion in the longer functional sections, especially on the right side. I’m increasing the generated symbol spacing while preserving the requested groups, sections, orientations, and pin order.

Visually inspected and cleaned the symbol. Increased spacing and shortened repeated group/section labels to PWR, CELL, ISNS, IF, FET, and GND, eliminating the visible label collisions while preserving pin order, orientation, numbering, and connectivity.

Already configured: PWR is the top section with Terminal Orders 1–3, and GND is the bottom section with Terminal Orders 9–10. The remaining groups are distributed between them.

I’ll render the current symbol and verify the visual spacing, section placement, pin labels, numbering, orientation, and ordering.

Rendered and verified the final symbol: all 21 pins are present with clear section separation and consistent spacing. PWR is at the top, GND at the bottom, left/right groups are distributed correctly, and pin numbers, labels, orientations, and orders are intact.