Operating junction temperature: 0 to 120 C; case temperature: 25 to 85 C.
PREXT and SREXT each require a 12.1 kOhm reference resistor to ground.
Pinout cross-check
Pins 1 through 48 match the datasheet pin numbers and functions. Duplicate supply and ground names use Flux-specific suffixes (_1, _2, etc.) but retain the correct physical pin numbers. Signal names for PCI Express, SATA, SPI, crystal, GPIO, reset, LED, and test mode match the datasheet.
The schematic-to-footprint name mapping is complete for all 49 current entries; no duplicate or missing mapped terminal names were found.
Symbol organization applied
All existing pin numbers, names, and footprint mappings were preserved. Pin Group was removed from every terminal. Unique terminal orders 1 through 49 were assigned with Power first and Ground last.
Table
Section
Pin count
Left / Right split
Power
15
7 / 8
PCI Express
7
4 / 3
SATA
8
4 / 4
Clock
2
1 / 1
SPI
4
2 / 2
GPIO and Control
5
3 / 2
Ground
8
4 / 4
Flagged mismatches and limitations
Pin descriptions are absent: all terminals lack the Pin Description property.
Pin electrical types are incomplete: all 49 terminals remain Unspecified, despite the datasheet defining input, output, bidirectional, power, ground, pull-up, pull-down, and differential roles.
Exposed-pad ambiguity: the datasheet calls the package QFN 48L and its pin table lists only pins 1-48. The current part adds EP as pin/pad 49. This is common footprint-library practice for an exposed thermal pad, but the attached datasheet does not explicitly assign it electrical pin number 49 or state its connection. Treat EP connectivity as Unclear / Check datasheet or package drawing before using it electrically.
Footprint geometry only partially verified: the footprint name is consistent with 7 mm x 7 mm, 0.50 mm pitch, 0.90 mm maximum height, and 49 numbered land entries. Exact perimeter land dimensions, exposed-pad land size, solder-mask/paste segmentation, and courtyard dimensions could not be independently read from the available indexed geometry.
Description is generic:PCI BUS CONTROLLER, CMOS should ideally be replaced with a specific functional description.
Visual rendering limitation: the project contains a custom symbol asset. Terminal Section, Pin Orientation, and Terminal Order metadata are now set, but the current custom asset may continue to control the rendered pin locations until the symbol is switched to a parametric style or the custom SVG is regenerated.
Recommended follow-up
Populate datasheet-derived Pin Description and Pin Type properties for all terminals.
Confirm the exposed-pad electrical connection from an authoritative package drawing, reference design, or manufacturer clarification.
Inspect the raw footprint land pattern against the QFN package dimensions and the intended assembly process.
Replace the generic description with: PCI Express Gen2 x1 to dual-port SATA 6 Gb/s controller.