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ADRV9002BBCZ Datasheet Verification Report
Date: 2026-07-20
Scope
Reviewed the available part metadata, schematic symbol terminals, footprint asset/pads, and datasheet-backed pin/package/spec information for the ADRV9002BBCZ part project.
Datasheet Source
Metadata Review

Table

FieldCurrent/available valueDatasheet/reference checkStatus
MPNADRV9002BBCZOrdering guide lists ADRV9002BBCZMatch
ManufacturerAnalog DevicesADI datasheet/product pageMatch
DescriptionDual Narrow-Band and Wideband RF TransceiverDatasheet title matchesMatch
Pin count196 terminals / 196 pads196-ball CSP_BGAMatch
PackageFootprint asset: BGA196C80P14X14_1200X1200X125.kicad_mod; 3D asset: ADRV9002BBCZ.stp12 mm × 12 mm, 196-ball CSP_BGA, package option BC-196-16Footprint asset appears consistent; package property missing
Part TypeIntegrated CircuitsRF transceiver ICAcceptable broad type
Part sub-type / IC typeLibrary search returned Logic, logicFunction: ANDDevice is an RF transceiver, not a logic AND gateMismatch
Datasheet URLhttps://www.analog.com/ADRV9002/datasheetOfficial ADI datasheet landing URLMatch
Machine Datasheet URLNot presentNot required, but absentMissing metadata
Package or Case CodeNot present as project-level propertyBC-196-16 / CSP_BGAMissing metadata
MountNot presentSurface-mount BGAMissing metadata
Key Datasheet Specs

Table

SpecDatasheet value
FunctionDual narrow-band and wideband RF transceiver
RF range30 MHz to 6000 MHz
Tx/Rx bandwidth12 kHz to 40 MHz
Package12 mm × 12 mm, 196-ball CSP_BGA
Package optionBC-196-16
Ball pitch0.80 mm BSC
Ball diameter0.40 mm to 0.50 mm
Body size11.90 mm to 12.10 mm square, 12.00 mm nominal
Ordering temperature range−40°C to +85°C
Nominal rails1.0 V, 1.3 V, 1.8 V domains
Absolute max, 1.0 V rails−0.2 V to +1.2 V
Absolute max, 1.3 V rails−0.2 V to +1.5 V
Absolute max, 1.8 V rails−0.3 V to +2.2 V
Input current to any non-supply pin±10 mA
Junction temperature range−40°C to +110°C
Storage temperature range−65°C to +150°C
Schematic Symbol Review
Summary
  • 196 terminal components are present.
  • Every terminal has a Pin Number property.
  • No duplicate Pin Number values were found.
  • All 196 terminals have Pin Type = Unspecified, despite the datasheet providing Input, Output, and Input/Output classifications.
  • No terminal has a populated Pin Description property.
  • The main fixed-function pin names generally match the datasheet ball assignments.
Pin Metadata Mismatches

Table

IssueImpactRecommendation
All terminal Pin Type values are UnspecifiedERC and downstream users cannot distinguish power, ground, inputs, outputs, bidirectional GPIO, RF ports, etc.Populate pin types from datasheet Table 17.
Pin Description is absent for every terminalUsers lose datasheet guidance such as bypass requirements, unused-pin instructions, supply noise sensitivity, and alternate modes.Populate Pin Description from datasheet Table 17.
AGPIO_XX_* names do not match datasheet Table 18 primary AGPIO numbersPin names are misleading and can cause firmware/schematic integration mistakes.Rename each AGPIO terminal to the exact datasheet primary function.
DGPIO_XX_* names do not match datasheet Table 19 primary DGPIO numbersDigital GPIO numbering is off by one and genericized, which can cause firmware pin mapping errors.Rename each DGPIO terminal to the exact datasheet primary function.
DGPIO_12/TX1__DCLK_OUT± and DGPIO_14/15/TX2__DCLK_OUT± include a double underscoreFunction is recognizable, but exact name does not match the datasheet.Remove the extra underscore before DCLK.
AGPIO Name Mismatches

Table

Current terminalBallDatasheet primary function
AGPIO_XX_1E3AGPIO_2
AGPIO_XX_2E12AGPIO_0
AGPIO_XX_3F4AGPIO_4
AGPIO_XX_4F5AGPIO_3
AGPIO_XX_5F10AGPIO_1
AGPIO_XX_6F11AGPIO_10
AGPIO_XX_7G4AGPIO_5
AGPIO_XX_8G6AGPIO_6
AGPIO_XX_9G9AGPIO_8
AGPIO_XX_10G11AGPIO_11
AGPIO_XX_11H6AGPIO_7
AGPIO_XX_12H9AGPIO_9
DGPIO Name Mismatches

Table

Current terminalBallDatasheet primary function
DGPIO_XX_1K6DGPIO_0
DGPIO_XX_2K7DGPIO_1
DGPIO_XX_3K8DGPIO_2
DGPIO_XX_4K9DGPIO_3
DGPIO_XX_5K10DGPIO_4
DGPIO_XX_6K11DGPIO_5
DGPIO_XX_7L4DGPIO_6
DGPIO_XX_8L5DGPIO_7
DGPIO_XX_9L6DGPIO_8
DGPIO_XX_10L9DGPIO_9
DGPIO_XX_11L10DGPIO_10
DGPIO_XX_12L11DGPIO_11
DGPIO_12/TX1__DCLK_OUT-M9DGPIO_12/TX1_DCLK_OUT−
DGPIO_13/TX1__DCLK_OUT+M10DGPIO_13/TX1_DCLK_OUT+
DGPIO_14/TX2__DCLK_OUT-M6DGPIO_14/TX2_DCLK_OUT−
DGPIO_15/TX2__DCLK_OUT+M5DGPIO_15/TX2_DCLK_OUT+
Footprint Review

Table

ItemObservedDatasheet checkStatus
Pad count196 pads196-ball packageMatch
Footprint nameBGA196C80P14X14_1200X1200X125.kicad_mod14 × 14 array, 0.80 mm pitch, 12.00 mm nominal bodyConsistent
Row/column pattern14 × 14 BGA grid using rows A-H, J, K, L, M, N, PDatasheet package drawing uses rows A-H, J, K, L, M, N, PMatch
Pad diameter/rule sizePad rule appears to encode ~0.41 mm circular padsDatasheet ball diameter is 0.40 mm to 0.50 mm; PCB land pattern can differ from ball diameterPlausible; verify against ADI/IPC land pattern before fabrication
Package metadata ruleFootprint node packageSize reports {0,0,0}Datasheet package is 12 mm × 12 mm × 1.09–1.25 mmMetadata incomplete, but asset name/geometry appear aligned
Overall Findings
The part is substantially identifiable as ADRV9002BBCZ and has the correct official datasheet link, manufacturer, pin count, footprint family, and broad description. The highest-risk issues are metadata quality issues rather than gross ball-map failures: missing pin descriptions, every pin type set to Unspecified, incorrect/generic AGPIO and DGPIO terminal names, and an incorrect library subtype/logic-function classification. These should be corrected before publishing or using this part in a larger schematic, especially because the AGPIO/DGPIO numbering affects firmware and board-level signal naming.
Remediation Update - 2026-07-20
Completed fixes requested after this review:
  • Renamed all AGPIO_XX_* terminals to the datasheet Table 18 primary names AGPIO_0 through AGPIO_11.
  • Renamed all DGPIO_XX_* terminals to the datasheet Table 19 primary names DGPIO_0 through DGPIO_11.
  • Removed the extra underscore from the alternate-function DGPIO names, for example DGPIO_13/TX1_DCLK_OUT+ and DGPIO_15/TX2_DCLK_OUT+.
  • Populated Pin Type on all 196 terminals; verification found 0 terminals still set to Unspecified.
  • Populated Pin Description on all 196 terminals; verification found 0 terminals missing a description.
  • Recorded package metadata in project metadata/description: 12 mm x 12 mm 196-ball CSP_BGA, package option BC-196-16, 0.80 mm BSC ball pitch, 0.40 mm to 0.50 mm ball diameter, surface-mount BGA.
Remaining limitation:
  • The available project-level metadata editor exposes package details through description/Implementation Details rather than a dedicated writable Package or Case Code project property in this part project. The package data is now recorded, but a dedicated part-level package field may still need library-side editing if Flux exposes that field separately.

  • Scope

  • Datasheet Source

  • Metadata Review

  • Key Datasheet Specs

  • Schematic Symbol Review

  • Summary

  • Pin Metadata Mismatches

  • AGPIO Name Mismatches

  • DGPIO Name Mismatches

  • Footprint Review

  • Overall Findings

  • Remediation Update - 2026-07-20