Part Verification Report
Thought for 6 sec
I’ll assign terminal order/orientation by the existing broad groups, then inspect the symbol metadata for consistency and report any remaining symbol-quality issues.
Worked for 4 mins 12 sec
Terminal order and orientation are applied. I’m running the symbol metadata review now to catch missing or inconsistent fields.
Worked for 2 mins 12 sec
Assigned
Terminal Order and Pin Orientation for all 196 terminals: Power = order 1/Top, RF = 2/Left, Clock and Sync = 3/Left, Auxiliary Analog = 4/Left, Control Interface = 5/Left, GPIO = 6/Right, Data Interface = 7/Right, Ground = 10/Bottom.Open items:
- Symbol metadata review passed: 0 missing terminal orders, 0 missing orientations, consistent order/orientation per group, and Section still matches Pin Group.
- Automated checks returned no open errors/warnings for the selected part/schematic review checks.
Suggested next steps:
- Visually review the regenerated symbol in the editor.
- Run a final full part review before publishing.
- If needed, refine individual within-group ordering for differential pairs and channel grouping.
Review and refine
Run final review
Refine pair ordering
Check symbol rendering
Verify footprint mapping
Refine this doc
Ask about this doc
ADRV9002BBCZ Datasheet Verification Report
Date: 2026-07-20
Scope
Reviewed the available part metadata, schematic symbol terminals, footprint asset/pads, and datasheet-backed pin/package/spec information for the ADRV9002BBCZ part project.
Datasheet Source
- Existing project Datasheet URL: https://www.analog.com/ADRV9002/datasheet
- Official ADI PDF located during review: https://www.analog.com/media/en/technical-documentation/data-sheets/adrv9002.pdf
- The Datasheet URL property was already populated, so it was not changed.
Metadata Review
Table
| Field | Current/available value | Datasheet/reference check | Status |
|---|---|---|---|
| MPN | ADRV9002BBCZ | Ordering guide lists ADRV9002BBCZ | Match |
| Manufacturer | Analog Devices | ADI datasheet/product page | Match |
| Description | Dual Narrow-Band and Wideband RF Transceiver | Datasheet title matches | Match |
| Pin count | 196 terminals / 196 pads | 196-ball CSP_BGA | Match |
| Package | Footprint asset: BGA196C80P14X14_1200X1200X125.kicad_mod; 3D asset: ADRV9002BBCZ.stp | 12 mm × 12 mm, 196-ball CSP_BGA, package option BC-196-16 | Footprint asset appears consistent; package property missing |
| Part Type | Integrated Circuits | RF transceiver IC | Acceptable broad type |
| Part sub-type / IC type | Library search returned Logic, logicFunction: AND | Device is an RF transceiver, not a logic AND gate | Mismatch |
| Datasheet URL | https://www.analog.com/ADRV9002/datasheet | Official ADI datasheet landing URL | Match |
| Machine Datasheet URL | Not present | Not required, but absent | Missing metadata |
| Package or Case Code | Not present as project-level property | BC-196-16 / CSP_BGA | Missing metadata |
| Mount | Not present | Surface-mount BGA | Missing metadata |
Key Datasheet Specs
Table
| Spec | Datasheet value |
|---|---|
| Function | Dual narrow-band and wideband RF transceiver |
| RF range | 30 MHz to 6000 MHz |
| Tx/Rx bandwidth | 12 kHz to 40 MHz |
| Package | 12 mm × 12 mm, 196-ball CSP_BGA |
| Package option | BC-196-16 |
| Ball pitch | 0.80 mm BSC |
| Ball diameter | 0.40 mm to 0.50 mm |
| Body size | 11.90 mm to 12.10 mm square, 12.00 mm nominal |
| Ordering temperature range | −40°C to +85°C |
| Nominal rails | 1.0 V, 1.3 V, 1.8 V domains |
| Absolute max, 1.0 V rails | −0.2 V to +1.2 V |
| Absolute max, 1.3 V rails | −0.2 V to +1.5 V |
| Absolute max, 1.8 V rails | −0.3 V to +2.2 V |
| Input current to any non-supply pin | ±10 mA |
| Junction temperature range | −40°C to +110°C |
| Storage temperature range | −65°C to +150°C |
Schematic Symbol Review
Summary
- 196 terminal components are present.
- Every terminal has a
Pin Numberproperty. - No duplicate
Pin Numbervalues were found. - All 196 terminals have
Pin Type = Unspecified, despite the datasheet providing Input, Output, and Input/Output classifications. - No terminal has a populated
Pin Descriptionproperty. - The main fixed-function pin names generally match the datasheet ball assignments.
Pin Metadata Mismatches
Table
| Issue | Impact | Recommendation |
|---|---|---|
All terminal Pin Type values are Unspecified | ERC and downstream users cannot distinguish power, ground, inputs, outputs, bidirectional GPIO, RF ports, etc. | Populate pin types from datasheet Table 17. |
Pin Description is absent for every terminal | Users lose datasheet guidance such as bypass requirements, unused-pin instructions, supply noise sensitivity, and alternate modes. | Populate Pin Description from datasheet Table 17. |
AGPIO_XX_* names do not match datasheet Table 18 primary AGPIO numbers | Pin names are misleading and can cause firmware/schematic integration mistakes. | Rename each AGPIO terminal to the exact datasheet primary function. |
DGPIO_XX_* names do not match datasheet Table 19 primary DGPIO numbers | Digital GPIO numbering is off by one and genericized, which can cause firmware pin mapping errors. | Rename each DGPIO terminal to the exact datasheet primary function. |
DGPIO_12/TX1__DCLK_OUT± and DGPIO_14/15/TX2__DCLK_OUT± include a double underscore | Function is recognizable, but exact name does not match the datasheet. | Remove the extra underscore before DCLK. |
AGPIO Name Mismatches
Table
| Current terminal | Ball | Datasheet primary function |
|---|---|---|
| AGPIO_XX_1 | E3 | AGPIO_2 |
| AGPIO_XX_2 | E12 | AGPIO_0 |
| AGPIO_XX_3 | F4 | AGPIO_4 |
| AGPIO_XX_4 | F5 | AGPIO_3 |
| AGPIO_XX_5 | F10 | AGPIO_1 |
| AGPIO_XX_6 | F11 | AGPIO_10 |
| AGPIO_XX_7 | G4 | AGPIO_5 |
| AGPIO_XX_8 | G6 | AGPIO_6 |
| AGPIO_XX_9 | G9 | AGPIO_8 |
| AGPIO_XX_10 | G11 | AGPIO_11 |
| AGPIO_XX_11 | H6 | AGPIO_7 |
| AGPIO_XX_12 | H9 | AGPIO_9 |
DGPIO Name Mismatches
Table
| Current terminal | Ball | Datasheet primary function |
|---|---|---|
| DGPIO_XX_1 | K6 | DGPIO_0 |
| DGPIO_XX_2 | K7 | DGPIO_1 |
| DGPIO_XX_3 | K8 | DGPIO_2 |
| DGPIO_XX_4 | K9 | DGPIO_3 |
| DGPIO_XX_5 | K10 | DGPIO_4 |
| DGPIO_XX_6 | K11 | DGPIO_5 |
| DGPIO_XX_7 | L4 | DGPIO_6 |
| DGPIO_XX_8 | L5 | DGPIO_7 |
| DGPIO_XX_9 | L6 | DGPIO_8 |
| DGPIO_XX_10 | L9 | DGPIO_9 |
| DGPIO_XX_11 | L10 | DGPIO_10 |
| DGPIO_XX_12 | L11 | DGPIO_11 |
| DGPIO_12/TX1__DCLK_OUT- | M9 | DGPIO_12/TX1_DCLK_OUT− |
| DGPIO_13/TX1__DCLK_OUT+ | M10 | DGPIO_13/TX1_DCLK_OUT+ |
| DGPIO_14/TX2__DCLK_OUT- | M6 | DGPIO_14/TX2_DCLK_OUT− |
| DGPIO_15/TX2__DCLK_OUT+ | M5 | DGPIO_15/TX2_DCLK_OUT+ |
Footprint Review
Table
| Item | Observed | Datasheet check | Status |
|---|---|---|---|
| Pad count | 196 pads | 196-ball package | Match |
| Footprint name | BGA196C80P14X14_1200X1200X125.kicad_mod | 14 × 14 array, 0.80 mm pitch, 12.00 mm nominal body | Consistent |
| Row/column pattern | 14 × 14 BGA grid using rows A-H, J, K, L, M, N, P | Datasheet package drawing uses rows A-H, J, K, L, M, N, P | Match |
| Pad diameter/rule size | Pad rule appears to encode ~0.41 mm circular pads | Datasheet ball diameter is 0.40 mm to 0.50 mm; PCB land pattern can differ from ball diameter | Plausible; verify against ADI/IPC land pattern before fabrication |
| Package metadata rule | Footprint node packageSize reports {0,0,0} | Datasheet package is 12 mm × 12 mm × 1.09–1.25 mm | Metadata incomplete, but asset name/geometry appear aligned |
Overall Findings
The part is substantially identifiable as ADRV9002BBCZ and has the correct official datasheet link, manufacturer, pin count, footprint family, and broad description. The highest-risk issues are metadata quality issues rather than gross ball-map failures: missing pin descriptions, every pin type set to
Unspecified, incorrect/generic AGPIO and DGPIO terminal names, and an incorrect library subtype/logic-function classification. These should be corrected before publishing or using this part in a larger schematic, especially because the AGPIO/DGPIO numbering affects firmware and board-level signal naming.Remediation Update - 2026-07-20
Completed fixes requested after this review:
- Renamed all
AGPIO_XX_*terminals to the datasheet Table 18 primary namesAGPIO_0throughAGPIO_11. - Renamed all
DGPIO_XX_*terminals to the datasheet Table 19 primary namesDGPIO_0throughDGPIO_11. - Removed the extra underscore from the alternate-function DGPIO names, for example
DGPIO_13/TX1_DCLK_OUT+andDGPIO_15/TX2_DCLK_OUT+. - Populated
Pin Typeon all 196 terminals; verification found 0 terminals still set toUnspecified. - Populated
Pin Descriptionon all 196 terminals; verification found 0 terminals missing a description. - Recorded package metadata in project metadata/description: 12 mm x 12 mm 196-ball CSP_BGA, package option BC-196-16, 0.80 mm BSC ball pitch, 0.40 mm to 0.50 mm ball diameter, surface-mount BGA.
Remaining limitation:
- The available project-level metadata editor exposes package details through description/Implementation Details rather than a dedicated writable
Package or Case Codeproject property in this part project. The package data is now recorded, but a dedicated part-level package field may still need library-side editing if Flux exposes that field separately.
Scope
Datasheet Source
Metadata Review
Key Datasheet Specs
Schematic Symbol Review
Summary
Pin Metadata Mismatches
AGPIO Name Mismatches
DGPIO Name Mismatches
Footprint Review
Overall Findings
Remediation Update - 2026-07-20
