Part Review and Datasheet Update

A

adrian95

Review all available part information (MPN, package, pin count, description, properties). If no datasheet URL is already set, search the web for the official datasheet and update the part's Datasheet property with the URL. Then cross-check the schematic symbol, footprint, and pin descriptions against the datasheet. Summarize key specs and flag any mismatches.

flux

I’ll inspect the part metadata, look for an official datasheet if needed, then compare the symbol/footprint/pin descriptions against the datasheet and report any mismatches.

flux

Completed the part review for 23AA02M-I/SN. I added the official Microchip datasheet URL plus missing Manufacturer Name and Part Type metadata, and created the full review report here: Part Review: 23AA02M-I/SN.
Open items:
  • Pin names/numbers match the datasheet.
  • Pin types and pin descriptions are still under-specified.
  • Footprint matches SOIC-8 /SN generally, but pad dimensions are slightly smaller than Microchip’s recommended land pattern.
Suggested next steps:
  1. Update terminal pin types and pin descriptions from the datasheet.
  2. Decide whether to revise the footprint to the exact Microchip recommended land pattern.
  3. Run part review checks again after metadata/pin cleanup.
Fix pins and footprint
Fix pin metadata
Revise land pattern
Rerun part checks
Add ordering properties
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Part Review: 23AA02M-I/SN
Sources
Current Part Metadata
  • MPN: 23AA02M-I/SN
  • Manufacturer: Microchip Technology
  • Part type: Integrated Circuit
  • Designator prefix: U
  • Description: SRAM - Synchronous Memory IC 2Mbit SPI - Quad I/O 143 MHz 7 ns 8-SOIC
  • Datasheet URL: set to official Microchip datasheet URL
  • Published part UID: f45e9838-52b3-4397-8c80-55f4c135f767
  • Pin count / pads: 8
Datasheet Key Specs
  • Device: 23AA02M, 2-Mbit serial SRAM
  • Supply voltage: 1.7 V to 3.6 V
  • Temperature grade: Industrial, -40°C to +85°C
  • Interfaces: SPI, SDI, SQI; SPI modes 0 and 3
  • Max clock: 143 MHz for high-speed operations; READ 0x03 limited to 40 MHz
  • Active current: 3 mA max at 40 MHz, 10 mA max at 143 MHz, VCC = 3.6 V
  • Standby current: 70 µA typical, 250 µA max at 85°C
  • Organization noted in datasheet as 256 x 8-bit; part is listed as 2048-Kbit / 2-Mbit SRAM
  • Package code /SN: 8-lead plastic SOIC, narrow 3.90 mm body
  • Package dimensions: 1.27 mm pitch, 4.90 mm body length, 3.90 mm molded body width, 6.00 mm overall lead span
  • Recommended land pattern: 1.27 mm pitch, 5.40 mm pad row spacing, 1.55 mm pad length, 0.60 mm pad width
Pinout Cross-Check

Table

PinDatasheet NameDatasheet FunctionCurrent SymbolResult
1CSChip Select*CSMatch, polarity marker differs from datasheet text but conveys active-low CS convention
2SO/SIO1Serial output; I/O in Dual/Quad modeSO/SIO1Match
3SIO2Quad I/O pin in Quad modeSIO2Match
4VSSGroundVSSMatch
5SI/SIO0Serial input; I/O in Dual/Quad modeSI/SIO0Match
6SCKSerial ClockSCKMatch
7HOLD/SIO3HOLD in SPI/SDI; I/O in Quad mode*HOLD/SIO3Match, polarity marker differs from datasheet text but conveys active-low HOLD convention
8VCC+1.7 V to +3.6 V supply for 23AA02MVCCMatch
Footprint Cross-Check
  • Footprint label: SOIC8_SN_MCH, consistent with Microchip /SN 8-lead narrow SOIC.
  • Pitch text in footprint: 0.05 in / 1.27 mm, matches datasheet.
  • Pad row spacing text: 0.209 in / 5.309 mm vs datasheet recommended 5.40 mm. Slightly smaller by about 0.09 mm.
  • Pad length text: 0.055 in / 1.397 mm vs datasheet recommended 1.55 mm. Smaller by about 0.15 mm.
  • Pad width text: 0.022 in / 0.559 mm vs datasheet recommended 0.60 mm. Smaller by about 0.04 mm.
Mismatches / Issues Flagged
  1. Project was missing Datasheet URL, Manufacturer Name, and Part Type; these were added.
  2. Terminal pin types are all set to Unspecified; recommend setting VCC as Power In, VSS as Ground, CS/SCK/HOLD as Input, SO/SIO1 as Output/Bi-Directional depending symbol convention, and SI/SIO0/SIO2 as Bi-Directional.
  3. Terminal pin descriptions are not populated beyond the pin names; recommend adding datasheet pin function descriptions.
  4. Footprint is the correct package family and pin count, but pad geometry appears slightly smaller than the Microchip recommended land pattern. This is likely usable for a generic SOIC-8, but if strict Microchip land-pattern compliance is desired, update pad length/width/row spacing to the datasheet recommended values.
Overall Assessment
The symbol pin numbering and names match the official datasheet for the 8-lead 23AA02M-I/SN. The footprint is correctly identified as 8-lead SOIC /SN narrow body with matching pitch, with only minor land-pattern dimensional deviations from Microchip's recommended pad geometry. The main remaining quality improvements are pin type and pin description metadata.

  • Sources

  • Current Part Metadata

  • Datasheet Key Specs

  • Pinout Cross-Check

  • Footprint Cross-Check

  • Mismatches / Issues Flagged

  • Overall Assessment