USB Mouse Switch PCB
Worked for 3 mins 51 sec
Added independent RESET and BOOT/FLASH buttons for both ESP32-S3 processors:
- SW1: U8 reset
- SW2: U8 flash/boot
- SW3: U9 reset
- SW4: U9 flash/boot
The isolated power domains remain separate, and the schematic review reports no electrical errors or warnings.
Remove the screen
Worked for 55 sec
Removed the OLED screen (
OLED1) from the schematic and PCB.The usb a is facing the board when it should be facing the other way
Worked for 1 min 35 sec
Fixed. The USB-A connector now faces outward, while remaining centered between the two USB-C connectors.
Review and place
Run PCB review
Place new buttons
Fix stackup issue
Check USB orientation
Update docs
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Project Specification
Project Overview
Status: Release-critical schematic remediation attempted; blocked by a platform canonical-net persistence defect described below. PCB placement/routing remains out of scope.
Intended Behavior
- PC1 sees a 1 ms / 1 kHz emulated or passed-through HID device.
- A physical mouse/keyboard attaches to the USB-A host port.
- PC2 controls behavior through a CH343 USB COM interface.
- Left MCU forwards modified HID descriptors/reports to PC1; right MCU hosts/parses the peripheral and handles commands.
Architecture
- U8: ESP32-S3-MINI-1-N4R2, PC1 native USB device.
- U9: ESP32-S3-MINI-1-N4R2, USB-A peripheral host.
- U10: CH343G USB-to-UART on PC2.
- Inter-MCU link: GPIO15-18, four independent signals, each with 4.7 kΩ series resistance to limit powered-off injection current to approximately (3.3-0.3)/4.7k = 0.64 mA maximum.
- Grounds are common for signaling. PC1 and PC2 VBUS rails are not intentionally tied.
Split Power Tree
- PC1: J1 VBUS → F1 500 mA PPTC → PC1_VBUS_PROT → U11 AP63203 → intended
3V3_LEFT→ U8 and left-domain support. - PC2: J2 VBUS → F3 1206L200PR → PC2_VBUS_PROT → U6 AP63203 (
3V3_RIGHT) plus U10 and U7/TPS2051C → USB-A VBUS. - No ideal-diode ORed shared
SYS_5Vrail remains; U4/U5 were removed. - TPS2051C provides explicit approximately 500 mA USB-A current limiting.
Independent Source Budgets
Table
| Source | Conservative allocation at 5 V input | Peak |
|---|---|---|
| PC1 | U8 500 mA at 3.3 V reflected at 88% = 375 mA; support/path margin = 50 mA | 425 mA |
| PC2 | U9 500 mA at 3.3 V reflected at 88% = 375 mA; CH343/control = 75 mA; USB-A current limit = 500 mA; margin/path loss = 100 mA | 1.05 A |
PC1 fits a post-enumeration USB 2.0 500 mA budget. PC2 does not fit default USB current. Normal operation requires J2 to be connected to a USB-C source advertising at least 1.5 A at 5 V. Firmware must disable U7 unless adequate advertised current is confirmed or a product-level fixed-source assumption is enforced. F3 is a 2 A-hold protection device and is not the policy limiter; U7 limits the peripheral branch.
UART Connectivity Intent
- CH343 command link only: U10.TXD ↔ U9.RXD0 and U9.TXD0 ↔ U10.RXD.
- U8 TXD0/RXD0 intentionally unused and marked no-connect.
- Inter-MCU data/flow control is separate on GPIO15-18 through R17/R7/R8/R18.
Canonical-Net Blocker
After deleting and rebuilding the affected UART and power nets with fresh names, readback returned two distinct canonical nets both named
3V3_LEFT: one contains U11/U8 and one contains U6/U9/U10. A requested 3V3_RIGHT readback is absent. This is a platform-level canonical persistence/name collision defect. Release is blocked until the two canonical rail identifiers can be made uniquely named and verified. No claim of completed power isolation is made while this defect remains.Interfaces
Both USB-C PC ports are USB 2.0 sinks with independent 5.1 kΩ Rd. USB data paths remain independent. USB-A uses TPS2051C current limiting.
PCB Requirements
Four layers classified as Top signal, L2 ground plane, L3 power plane, Bottom signal. All USB pairs target 90 Ω differential with continuous ground reference. Placement and routing were not attempted in this pass.
Project Overview
Intended Behavior
Architecture
Split Power Tree
Independent Source Budgets
UART Connectivity Intent
Canonical-Net Blocker
Interfaces
PCB Requirements
