USB Mouse Switch PCB
Worked for 3 mins 51 sec
Added independent RESET and BOOT/FLASH buttons for both ESP32-S3 processors:
- SW1: U8 reset
- SW2: U8 flash/boot
- SW3: U9 reset
- SW4: U9 flash/boot
The isolated power domains remain separate, and the schematic review reports no electrical errors or warnings.
Remove the screen
Worked for 55 sec
Removed the OLED screen (
OLED1) from the schematic and PCB.The usb a is facing the board when it should be facing the other way
Worked for 1 min 35 sec
Fixed. The USB-A connector now faces outward, while remaining centered between the two USB-C connectors.
Review and place
Run PCB review
Place new buttons
Fix stackup issue
Check USB orientation
Update docs
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Design Notes
Focused release-critical remediation pass
Changes made
- Removed the former shared-source ORing architecture (U4/U5 and
SYS_5V). - Added U11 AP63203 with L2/C36-C39 as a dedicated PC1-to-3V3 left-domain regulator.
- Retained U6 as the PC2/right-domain regulator and connected U7 USB-A power switch to PC2 only.
- Replaced PC2 F2 500 mA PPTC with F3 1206L200PR (2 A hold). This is protection sizing, not permission to draw 2 A.
- Added 4.7 kΩ series resistors R17, R7, R8, R18 on all four inter-MCU UART/flow-control lines. Worst-case powered-off injection is approximately 0.64 mA per asserted line.
- Deleted/rebuilt PC2 UART nets; U8 TXD0/RXD0 were disconnected and marked no-connect.
- Removed RP2040/CH9102 active components previously; no such components remain in component search. Some obsolete portal text associated with removed U4/U5/F2 remains in canonical/visual readback and must be cleaned after the platform persistence issue is resolved.
- Corrected four-layer classification to Top signal / L2 ground / L3 power / Bottom signal. No placement or routing was performed.
Per-port budgets
- PC1: U8 peak 500 mA @3.3 V → 375 mA @5 V at 88%; plus 50 mA margin = 425 mA peak. F1 500 mA hold is retained. Requires normal USB enumeration before full operation.
- PC2: U9 peak reflected = 375 mA; CH343/control = 75 mA; USB-A branch limited to 500 mA; margin = 100 mA; total 1.05 A peak. Requires USB-C advertised current ≥1.5 A at 5 V. Firmware must keep U7 disabled if adequate source current is not established.
Release blocker: canonical persistence defect
Fresh-net rebuild did not produce stable unique power-net identity. Bounded readback shows:
3V3_LEFTcontaining U11, L2, U8, C30/C31, R13/R15 and C37/C38.- A second distinct
3V3_LEFTcontaining U6, L1, U9, U10, right-domain passives and support loads. 3V3_RIGHTis absent in the readback despite a successful rename response.
This prevents trustworthy proof that the PC1 and PC2 3.3 V domains are uniquely represented. Per instruction, remediation stopped rather than claiming completion. Exact UART pin memberships must also be re-read after the rail identity defect is repaired.
Bounded verification status
- RP2040/CH9102 component-name search: zero components.
- New regulator and four series resistors were wired; immediate mutation checks resolved their floating-pin findings.
- Final ERC/connectivity sign-off is not complete because canonical rail identity is defective.
- Physical DRC findings (F3/D5 outside board and high density) were not remediated because placement/routing was explicitly out of scope.
Focused release-critical remediation pass
Changes made
Per-port budgets
Release blocker: canonical persistence defect
Bounded verification status
