BQ25185 Charger Topology
Thought for 48 sec
El adjunto solicita sólo un documento de cierre de ingeniería. Crearé el plan único con progreso 0–100%, decisiones abiertas, bloqueos y paquete de exportación previsto, sin modificar el diseño ni generar archivos de fabricación.
Thought for 29 sec
Estado consolidado: la arquitectura y documentación están avanzadas, pero las decisiones físicas/eléctricas y varios componentes exactos impiden cerrar PCB/fabricación. Crearé el plan de 80% con el backlog ordenado.
Worked for 25 sec
Created a project doc
Brand NewDay — Flux 80 Percent Completion Plan
Mandatory state: BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION Scope: Engineering closure backlog only. No schematic, PCB, nets, B...
Fase 3 completada sin modificar esquema, PCB, nets, BOM, librerías, placement ni routing.
El plan muestra el avance 0–100%, el estado completo en Flux, decisiones que debe definir el usuario, bloqueos de EasyEDA, paquete final previsto y la secuencia de cierre de 80% a 100%. El estado permanece BENCH_ONLY / 0% fabrication release.
Prepare export package
Fix library gaps
Select passive MPNs
Review closure risks
Plan next schematic fixes
Refine this doc
Ask about this doc
EasyEDA Manual Reconstruction Manifest — Brand NewDay
Status: BENCH_ONLY / NOT FOR FABRICATION / NOT FOR ENERGIZATION
Source: Current Flux schematic/netlist plus Phase 1–2.3 reports.
Scope: Documentation only. No schematic, PCB, nets, BOM, library, placement, or routing changes were made.
Source: Current Flux schematic/netlist plus Phase 1–2.3 reports.
Scope: Documentation only. No schematic, PCB, nets, BOM, library, placement, or routing changes were made.
Critical Reconstruction Rules
- Preserve AIRTAG_CHG_SYS = U3 pin 1 SYS + C5 pin 1 only.
- Connect U3 pin 4 CE directly to AIRTAG_PACK_NEG/GND. Never connect CE to SYS.
- Use the official MCP41HV51-503E/ST pinout below, not the current MCP45HV proxy pin numbering.
- Use the official G5LE-14-DC5 pinout below. The current Flux relay proxy wiring is mismatched and must not be copied.
- Q2/Q3 remain DNP / BENCH_ONLY, with every terminal unconnected.
- Relay contacts remain external/open. Do not connect any machine/load.
- RF nets remain open; do not invent antenna or matching circuitry.
- LM5069 UVLO/OVLO/TIMER/PWR networks remain open until real input/load limits exist.
Block 1 — USB-C Service / ESD / USB-UART
Component List
Table
| Designator | Exact MPN / value | Package / EasyEDA footprint target | State |
|---|---|---|---|
| J1 | DX07S016JA3R1500 | Exact JAE JA3 footprint from drawing SJ122206; 16-position USB-C, shell-DIP 1.2 mm | LIBRARY GAP; logical proxy usable, proxy footprint mismatched |
| U1 | TPD4E02B04DQAR | USON-10, 2.5 × 1.0 mm, 0.5 mm pitch | Populated |
| U2 | CP2102N-A02-GQFN28 | QFN-28, 5 × 5 mm, exposed pad | Populated |
| C1 | 100 nF | 0603 / 1608 metric | Populated |
| C2 | 4.7 µF | 0603 / 1608 metric | Populated |
| R1 | 5.1 kΩ, 1% | 0603 / 1608 metric | Populated |
| R2 | 5.1 kΩ, 1% | 0603 / 1608 metric | Populated |
| R3 | 22.1 kΩ, 1% | 0603 / 1608 metric | Populated |
| R4 | 47.5 kΩ, 1% | 0603 / 1608 metric | Populated |
| R5 | 1 kΩ, 1% | 0603 / 1608 metric | Populated |
Pin-to-Net
J1 — DX07S016JA3R1500 logical mapping
Table
| Pin | Signal | Net / state |
|---|---|---|
| 1 | GND | DGND_SERVICE |
| 2 | VBUS | USB_VBUS_RAW |
| 3 | CC1 | USB_CC1 |
| 4 | SBU2 | NC/open |
| 5 | D− | USB_D_N |
| 6 | D+ | USB_D_P |
| 7 | D+ duplicate | USB_D_P |
| 8 | D− duplicate | USB_D_N |
| 9 | CC2 | USB_CC2 |
| 10 | SBU1 | NC/open |
| 11 | VBUS duplicate | USB_VBUS_RAW |
| 12 | GND duplicate | DGND_SERVICE |
| S1–S6 | Shield tabs | DGND_SERVICE |
U1 — TPD4E02B04DQAR
Table
| Pin | Function | Net / state |
|---|---|---|
| 1 | IO1 | USB_D_P |
| 2 | IO2 | USB_D_N |
| 3 | GND | DGND_SERVICE |
| 4 | IO3 | USB_CC1 |
| 5 | IO4 | USB_CC2 |
| 6, 7, 9, 10 | NC | NC/open |
| 8 | GND | DGND_SERVICE |
U2 — CP2102N-A02-GQFN28
Table
| Pin | Function | Net / state |
|---|---|---|
| 1 | DCD | NC/open |
| 2 | RI/CLK | NC/open |
| 3 | GND | DGND_SERVICE |
| 4 | D+ | USB_D_P |
| 5 | D− | USB_D_N |
| 6 | VDD | RX_3V3 |
| 7 | VREGIN | RX_3V3 |
| 8 | VBUS | USB_VBUS_RAW |
| 9 | RSTB | CP2102N_RSTB |
| 10 | NC | NC |
| 11 | SUSPENDB | NC/open |
| 12 | SUSPEND | NC/open |
| 13 | CHREN | NC/open |
| 14 | CHR1 | NC/open |
| 15 | CHR0 | NC/open |
| 16 | GPIO.3/WAKEUP | NC/open |
| 17 | GPIO.2/RS485 | NC/open |
| 18 | GPIO.1/RXT | NC/open |
| 19 | GPIO.0/TXT | NC/open |
| 20 | GPIO.6 | NC/open |
| 21 | GPIO.5 | NC/open |
| 22 | GPIO.4 | NC/open |
| 23 | CTS | NC/open |
| 24 | RTS | NC/open |
| 25 | RXD | USB_UART_RXD_MCU_TX |
| 26 | TXD | USB_UART_TXD_MCU_RX |
| 27 | DSR | NC/open |
| 28 | DTR | NC/open |
| 29 / EP | BGND | DGND_SERVICE |
Passives
Table
| Component | Pin 1 | Pin 2 |
|---|---|---|
| C1 | RX_3V3 | DGND_SERVICE |
| C2 | RX_3V3 | DGND_SERVICE |
| R1 | USB_CC1 | DGND_SERVICE |
| R2 | USB_CC2 | DGND_SERVICE |
| R3 | USB_VBUS_RAW | USB_VBUS_SENSE_OPEN |
| R4 | USB_VBUS_SENSE_OPEN | DGND_SERVICE |
| R5 | CP2102N_RSTB | RX_3V3 |
Block 2 — BQ25185 Charger / Battery Protection / AirTag Buck-Boost
Component List
Table
| Designator | Exact MPN / value | Package / footprint | State |
|---|---|---|---|
| U3 | BQ25185DLHR | DLH0010A WSON-10 + exposed pad | Populated; pinout verified |
| U4 | BQ29700DSER | WSON-6, 1.5 × 1.5 mm, 0.5 mm pitch | Populated |
| U8 | TPS63030DSKR | DSK0010A VSON/WSON-10, 2.5 × 2.5 mm, 0.5 mm, EP 1.2 × 2.0 mm | Proxy VERIFIED; R suffix is reel quantity |
| L2 | 2.2 µH | 0805 / 2012 metric | Populated; exact MPN not defined |
| C3 | 47 pF C0G | 0603 | Populated |
| C4 | 1 µF, 25 V | 0603 | Populated |
| C5 | 10 µF, 25 V | 0805 | Populated; SYS cap |
| C6 | 1 µF, 10 V | 0603 | Populated |
| C7 | 100 nF | 0603 | Populated |
| C13 | 10 µF, 6.3 V | 0805 | Populated |
| C14 | 22 µF, 6.3 V | 0805 | Populated |
| R6 | 24 kΩ, 1% | 0603 | Populated; 4.2 V / ILIM 100 mA program |
| R7 | 21.5 kΩ, 1% | 0603 | Populated; charge current ≈14 mA typ |
| R8 | 2.2 kΩ, 1% | 0603 | Populated |
| R14 | 1 MΩ, 1% | 0603 | Populated |
| R15 | 200 kΩ, 1% | 0603 | Populated |
| R25 | 10 kΩ | 0603 | Populated |
Pin-to-Net
U3 — BQ25185DLHR
Table
| Pin | Function | Net / state |
|---|---|---|
| 1 | SYS | AIRTAG_CHG_SYS |
| 2 | BAT | AIRTAG_CELL_POS |
| 3 | STAT2 | NC/open |
| 4 | CE active-low | AIRTAG_PACK_NEG — explicit GND; never SYS |
| 5 | GND | AIRTAG_PACK_NEG |
| 6 | TS/MR | BQ25185_TS_MR |
| 7 | ILIM/VSET | BQ25185_VSET_PROG |
| 8 | ISET | BQ25185_ISET_PROG |
| 9 | STAT1 | NC/open |
| 10 | IN | AIRTAG_CHG_5V |
| 11 / EP | Exposed pad | AIRTAG_PACK_NEG |
U4 — BQ29700DSER
Table
| Pin | Function | Net / state |
|---|---|---|
| 1 | NC | NC |
| 2 | COUT | NC/open — protection FET network not defined |
| 3 | DOUT | NC/open — protection FET network not defined |
| 4 | VSS | AIRTAG_CELL_NEG |
| 5 | BAT | AIRTAG_CELL_POS |
| 6 | V− | BQ29700_V_MINUS |
U8 — TPS63030DSKR
Table
| Pin | Function | Net / state |
|---|---|---|
| 1 | VOUT | AIRTAG_3V0 |
| 2 | L2 | AIRTAG_BUCK_L2 |
| 3 | PGND | AIRTAG_PACK_NEG |
| 4 | L1 | AIRTAG_BUCK_L1 |
| 5 | VIN | AIRTAG_CELL_POS |
| 6 | EN | AIRTAG_CELL_POS |
| 7 | PS/SYNC | OPEN in current state; Phase 2 proposes GND for power-save |
| 8 | VINA | AIRTAG_CELL_POS |
| 9 | GND | AIRTAG_PACK_NEG |
| 10 | FB | AIRTAG_FB |
| EP / pad 11 | PGND | AIRTAG_PACK_NEG |
Passives
Table
| Component | Pin 1 | Pin 2 |
|---|---|---|
| C3 | BQ25185_ISET_PROG | AIRTAG_PACK_NEG |
| C4 | AIRTAG_CHG_5V | AIRTAG_PACK_NEG |
| C5 | AIRTAG_CHG_SYS | AIRTAG_PACK_NEG |
| C6 | AIRTAG_CELL_POS | AIRTAG_PACK_NEG |
| C7 | AIRTAG_CELL_POS | AIRTAG_CELL_NEG |
| C13 | AIRTAG_CELL_POS | AIRTAG_PACK_NEG |
| C14 | AIRTAG_3V0 | AIRTAG_PACK_NEG |
| R6 | BQ25185_VSET_PROG | AIRTAG_PACK_NEG |
| R7 | BQ25185_ISET_PROG | AIRTAG_PACK_NEG |
| R8 | BQ29700_V_MINUS | AIRTAG_PACK_NEG |
| R14 | AIRTAG_3V0 | AIRTAG_FB |
| R15 | AIRTAG_FB | AIRTAG_PACK_NEG |
| R25 | BQ25185_TS_MR | AIRTAG_PACK_NEG |
| L2 | AIRTAG_BUCK_L1 | AIRTAG_BUCK_L2 |
Battery Decision State
- Battery: OPEN/TBD. Use only a 1S chemistry compatible with 4.2 V regulation.
- R6=24 kΩ programs 4.2 V charge regulation and 100 mA input limit.
- R7=21.5 kΩ programs approximately 14 mA typical charge current.
- Do not energize until battery chemistry, capacity, protection and C-rate are confirmed.
Block 3 — Protected High-Voltage Input / 5 V Buck / 3.3 V LDO
Component List
Table
| Designator | Exact MPN / value | Package / footprint | State |
|---|---|---|---|
| U6 | LM5069MM-1/NOPB | DGS VSSOP-10 | Proxy LM5069MMX-1 VERIFIED; reel difference only |
| Q1 | CSD19536KTT | TO-263-3 / DDPAK | Populated |
| R9 | 0.100 Ω, 1 W | 2512 / 6332 metric | Populated |
| R10 | 100 kΩ | 0603 | Populated |
| U7 | LM5164DDAR | PowerSOIC-8 / SO-8 EP, DDA | Populated |
| L1 | MSS1246T-683MLB, 68 µH ±20% | Exact Coilcraft 12 × 12 × 4.6 mm; pads ≈5.5 × 5.0 mm, 4.0 mm inner gap | Current generic footprint invalid; exact spec verified |
| C10 | 2.2 µF, 100 V | 1210 | Populated |
| C11 | 2.2 nF, 50 V | 0603 | Populated |
| C12 | 22 µF, 25 V | 1210 | Populated |
| R11 | 42.2 kΩ | 0603 | Populated |
| R12 | 100 kΩ | 0603 | Populated |
| R13 | 31.6 kΩ | 0603 | Populated |
| U5 | TPS7A2033PDBVR | SOT-23-5 | Populated |
| C8 | 1 µF, 10 V | 0603 | Populated |
| C9 | 1 µF, 10 V | 0603 | Populated |
Pin-to-Net
U6 — LM5069MM-1/NOPB
Table
| Pin | Function | Net / state |
|---|---|---|
| 1 | SENSE | VIN_SENSE |
| 2 | VIN | VIN_RAW |
| 3 | UVLO | LM5069_UVLO_OPEN |
| 4 | OVLO | LM5069_OVLO_OPEN |
| 5 | GND | DGND_SERVICE |
| 6 | TIMER | LM5069_TIMER_OPEN |
| 7 | PWR | LM5069_PWRSET_OPEN |
| 8 | PGD | MACHINE_POWER_GOOD |
| 9 | OUT | VIN_PROTECTED |
| 10 | GATE | Q_HS1_GATE |
Q1 — CSD19536KTT
Table
| Pin | Function | Net |
|---|---|---|
| 1 | Gate | Q_HS1_GATE |
| 2 | Drain | VIN_RAW |
| 3 | Source | VIN_PROTECTED |
U7 — LM5164DDAR
Table
| Pin | Function | Net |
|---|---|---|
| 1 | GND | DGND_SERVICE |
| 2 | VIN | VIN_PROTECTED |
| 3 | EN/UVLO | MACHINE_POWER_GOOD |
| 4 | RON | LM5164_RON |
| 5 | FB | LM5164_FB |
| 6 | PGOOD | MACHINE_POWER_GOOD |
| 7 | BST | LM5164_BST |
| 8 | SW | LM5164_SW |
| 9 / EP | Exposed pad | DGND_SERVICE |
L1 — MSS1246T-683MLB
Table
| Pin | Function | Net |
|---|---|---|
| 1 | Passive terminal | LM5164_SW |
| 2 | Passive terminal | RX_5V |
Verified component data: 68 µH ±20%; DCR 167 mΩ typ / 186 mΩ max; Isat up to 2.3/2.5/2.7 A; Irms 1.3/1.8 A. Non-polarized.
U5 — TPS7A2033PDBVR
Table
| Pin | Function | Net / state |
|---|---|---|
| 1 | IN | RX_5V |
| 2 | GND | DGND_SERVICE |
| 3 | EN | RX_5V |
| 4 | NC | NC |
| 5 | OUT | RX_3V3 |
Passives
Table
| Component | Pin 1 | Pin 2 |
|---|---|---|
| R9 | VIN_RAW | VIN_SENSE |
| R10 | RX_5V | MACHINE_POWER_GOOD |
| C10 | VIN_PROTECTED | DGND_SERVICE |
| C11 | LM5164_BST | LM5164_SW |
| C12 | RX_5V | DGND_SERVICE |
| R11 | VIN_PROTECTED | LM5164_RON |
| R12 | RX_5V | LM5164_FB |
| R13 | LM5164_FB | DGND_SERVICE |
| C8 | RX_5V | DGND_SERVICE |
| C9 | RX_3V3 | DGND_SERVICE |
Open LM5069 Networks
- LM5069_UVLO_OPEN: U6.3 only.
- LM5069_OVLO_OPEN: U6.4 only.
- LM5069_TIMER_OPEN: U6.6 only.
- LM5069_PWRSET_OPEN: U6.7 only.
- These require real VIN limits, output capacitance, inrush, load and MOSFET SOA before values are selected.
Block 4 — CC1354P106 Controller / UART / SPI / RF
Component List
Table
| Designator | Exact MPN / value | Package / footprint | State |
|---|---|---|---|
| U9 | CC1354P106T0RGZR | RGZ VQFN-48, 7 × 7 mm, 0.5 mm pitch, exposed ground pad | Proxy pinout/footprint VERIFIED; use exact MPN in EasyEDA |
| C15 | 22 µF, 6.3 V | 0805 | Populated |
| C16 | 100 nF | 0402 | Populated |
| C17 | 100 nF | 0402 | Populated |
| C18 | 100 nF | 0402 | Populated |
| R16 | 10 kΩ | 0402 | Populated |
U9 Pin-to-Net
Table
| Pin | Signal | Net / state |
|---|---|---|
| 1 | RF_P_2_4GHZ | NC/open |
| 2 | RF_N_2_4GHZ | NC/open |
| 3 | RF_P_SUB_1GHZ | RF915_P_OPEN |
| 4 | RF_N_SUB_1GHZ | RF915_N_OPEN |
| 5 | TX_20DBM_P | RF_PA20_P_OPEN |
| 6 | TX_20DBM_N | RF_PA20_N_OPEN |
| 7 | RX_TX | NC/open |
| 8 | X32K_Q1 | NC/open |
| 9 | X32K_Q2 | NC/open |
| 10 | DIO_5 | USB_UART_RXD_MCU_TX |
| 11 | DIO_6 | USB_UART_TXD_MCU_RX |
| 12 | DIO_7 | MCP_SPI_SCK |
| 13 | VDDS2 | RX_3V3 |
| 14 | DIO_8 | MCP_SPI_CS_N |
| 15 | DIO_9 | MCP_SPI_MOSI |
| 16 | DIO_10 | MCP_SPI_MISO |
| 17–21 | DIO_11–DIO_15 | NC/open |
| 22 | VDDS3 | RX_3V3 |
| 23 | DCOUPL | CC1354_DCOUPL |
| 24 | JTAG_TMSC | NC/open |
| 25 | JTAG_TCKC | NC/open |
| 26 | DIO_16 | RELAY_K1_DRIVE |
| 27 | DIO_17 | RELAY_K2_DRIVE |
| 28 | DIO_18 | RELAY_K3_DRIVE |
| 29–32 | DIO_19–DIO_22 | NC/open |
| 33 | DCDC_SW | NC/open |
| 34 | VDDS_DCDC | RX_3V3 |
| 35 | RESET_N | CC1354_RESET_N |
| 36–43 | DIO_23–DIO_30 | NC/open |
| 44 | VDDS | RX_3V3 |
| 45 | VDDR | CC1354_VDDR |
| 46 | X48M_N | NC/open |
| 47 | X48M_P | NC/open |
| 48 | VDDR_RF | CC1354_VDDR |
| EP / 49 | Ground pad | DGND_SERVICE |
Passives
Table
| Component | Pin 1 | Pin 2 |
|---|---|---|
| C15 | RX_3V3 | DGND_SERVICE |
| C16 | RX_3V3 | DGND_SERVICE |
| C17 | RX_3V3 | DGND_SERVICE |
| C18 | CC1354_DCOUPL | DGND_SERVICE |
| R16 | RX_3V3 | CC1354_RESET_N |
RF915_N/P and RF_PA20_N/P are intentionally open. Do not add an antenna or matching network.
Block 5 — MCP41HV51 Digital Potentiometer
Component List
Table
| Designator | Exact MPN / value | Package / footprint | State |
|---|---|---|---|
| U10 | MCP41HV51-503E/ST, SPI, 50 kΩ | TSSOP-14, 4.4 mm body class, 0.65 mm pitch | Exact part required; current Flux MCP45HV proxy is unsafe |
| C19 | 100 nF | 0603 | Populated |
| R17 | 10 kΩ | 0603 | CS pull-up |
| R18 | 10 kΩ | 0603 | SHDN pull-down |
Official U10 Pin-to-Net for EasyEDA
Use this mapping. Do not copy the current proxy pin numbers.
Table
| Pin | Official MCP41HV51 function | Intended net / state |
|---|---|---|
| 1 | VL | RX_3V3 |
| 2 | CS | MCP_SPI_CS_N |
| 3 | SCK | MCP_SPI_SCK |
| 4 | SDI | MCP_SPI_MOSI |
| 5 | SDO | MCP_SPI_MISO |
| 6 | WLAT | NC/open |
| 7 | SHDN | MCP_SHDN_SAFE_N |
| 8 | DGND | DGND_SERVICE |
| 9 | V− | OPEN — analog supply not defined |
| 10 | P0B | OPEN — external analog terminal not defined |
| 11 | P0W | OPEN — wiper/load not defined |
| 12 | P0A | OPEN — external analog terminal not defined |
| 13 | V+ | OPEN — analog supply not defined |
| 14 | NC | NC |
Support Passives
Table
| Component | Pin 1 | Pin 2 |
|---|---|---|
| C19 | RX_3V3 | DGND_SERVICE |
| R17 | RX_3V3 | MCP_SPI_CS_N |
| R18 | MCP_SHDN_SAFE_N | DGND_SERVICE |
The existing Flux proxy places SHDN/DGND/V−/P0 terminals one pin later than the exact SPI part. The table above is the authoritative reconstruction mapping.
Block 6 — Three Relay Driver Channels
Exact Relay Specification
K1/K2/K3 target MPN: Omron G5LE-14-DC5, fully sealed SPDT/1c PCB relay, 5 VDC coil, approximately 79.4 mA, 63 Ω, 400 mW. Body max approximately 22.5 × 16.5 × 19.0 mm. Use official Omron five-hole through-hole footprint.
Official G5LE-14-DC5 pins
Table
| Pin | Function |
|---|---|
| 1 | COM / movable contact |
| 2 | Coil |
| 3 | NO contact |
| 4 | NC contact |
| 5 | Coil |
Important: The current Flux proxy incorrectly treats pin 4 as a coil terminal. For manual EasyEDA reconstruction use the official mapping below.
Channel K1
Table
| Component | Exact part/value | Package | Pin-to-net / state |
|---|---|---|---|
| K1 | G5LE-14-DC5 | Omron G5LE TH | 5=RX_5V; 2=RELAY_K1_COIL_NEG; 1/3/4=external OPEN |
| Q4 | CSD13380F3 | PICOSTAR/YJM 3-pin | 1 G=RELAY_K1_GATE; 2 S=DGND_SERVICE; 3 D=RELAY_K1_COIL_NEG |
| D1 | PMEG2010AEB | SOD-523 | 1 K=RX_5V; 2 A=RELAY_K1_COIL_NEG |
| R19 | 1 kΩ, 1% | 0603 | 1=RELAY_K1_DRIVE; 2=RELAY_K1_GATE |
| R22 | 10 kΩ, 1% | 0603 | 1=RELAY_K1_GATE; 2=DGND_SERVICE |
U9 pin 26 DIO_16 connects to RELAY_K1_DRIVE.
Channel K2
Table
| Component | Exact part/value | Package | Pin-to-net / state |
|---|---|---|---|
| K2 | G5LE-14-DC5 | Omron G5LE TH | 5=RX_5V; 2=RELAY_K2_COIL_NEG; 1/3/4=external OPEN |
| Q5 | CSD13380F3 | PICOSTAR/YJM 3-pin | 1 G=RELAY_K2_GATE; 2 S=DGND_SERVICE; 3 D=RELAY_K2_COIL_NEG |
| D2 | PMEG2010AEB | SOD-523 | 1 K=RX_5V; 2 A=RELAY_K2_COIL_NEG |
| R20 | 1 kΩ, 1% | 0603 | 1=RELAY_K2_DRIVE; 2=RELAY_K2_GATE |
| R23 | 10 kΩ, 1% | 0603 | 1=RELAY_K2_GATE; 2=DGND_SERVICE |
U9 pin 27 DIO_17 connects to RELAY_K2_DRIVE.
Channel K3
Table
| Component | Exact part/value | Package | Pin-to-net / state |
|---|---|---|---|
| K3 | G5LE-14-DC5 | Omron G5LE TH | 5=RX_5V; 2=RELAY_K3_COIL_NEG; 1/3/4=external OPEN |
| Q6 | CSD13380F3 | PICOSTAR/YJM 3-pin | 1 G=RELAY_K3_GATE; 2 S=DGND_SERVICE; 3 D=RELAY_K3_COIL_NEG |
| D3 | PMEG2010AEB | SOD-523 | 1 K=RX_5V; 2 A=RELAY_K3_COIL_NEG |
| R21 | 1 kΩ, 1% | 0603 | 1=RELAY_K3_DRIVE; 2=RELAY_K3_GATE |
| R24 | 10 kΩ, 1% | 0603 | 1=RELAY_K3_GATE; 2=DGND_SERVICE |
U9 pin 28 DIO_18 connects to RELAY_K3_DRIVE.
Relay contacts are not connected to any machine or load. Keep COM/NO/NC pins open and labelled external.
Block 7 — Experimental DNP Paths
Table
| Designator | MPN | Package | Pin state | Population state |
|---|---|---|---|---|
| Q2 | CSD16406Q3 | DFN-8, 3.3 × 3.3 mm, 0.65 mm pitch + EP | Pins 1/2/3 S, pin 4 G, pins 5/6/7/8 D, pin 9 EP: all NC/open | DNP / BENCH_ONLY / exclude from P&P |
| Q3 | CSD16406Q3 | DFN-8, 3.3 × 3.3 mm, 0.65 mm pitch + EP | Pins 1/2/3 S, pin 4 G, pins 5/6/7/8 D, pin 9 EP: all NC/open | DNP / BENCH_ONLY / exclude from P&P |
Complete Net Membership Summary
Table
| Net | Members / state |
|---|---|
| USB_VBUS_RAW | J1.2, J1.11, U2.8, R3.1 |
| USB_CC1 | J1.3, U1.4, R1.1 |
| USB_CC2 | J1.9, U1.5, R2.1 |
| USB_D_P | J1.6, J1.7, U1.1, U2.4 |
| USB_D_N | J1.5, J1.8, U1.2, U2.5 |
| USB_VBUS_SENSE_OPEN | R3.2, R4.1 — open destination |
| CP2102N_RSTB | U2.9, R5.1 |
| USB_UART_TXD_MCU_RX | U2.26, U9.11 |
| USB_UART_RXD_MCU_TX | U2.25, U9.10 |
| AIRTAG_CHG_5V | U3.10, C4.1 — source open/TBD |
| AIRTAG_CHG_SYS | U3.1, C5.1 only |
| AIRTAG_CELL_POS | U3.2, U4.5, U8.5, U8.6, U8.8, C6.1, C7.1, C13.1 |
| AIRTAG_CELL_NEG | U4.4, C7.2 |
| BQ29700_V_MINUS | U4.6, R8.1 |
| BQ25185_ISET_PROG | U3.8, C3.1, R7.1 |
| BQ25185_VSET_PROG | U3.7, R6.1 |
| BQ25185_TS_MR | U3.6, R25.1 |
| AIRTAG_BUCK_L1 | U8.4, L2.1 |
| AIRTAG_BUCK_L2 | U8.2, L2.2 |
| AIRTAG_3V0 | U8.1, C14.1, R14.1 |
| AIRTAG_FB | U8.10, R14.2, R15.1 |
| VIN_RAW | U6.2, R9.1, Q1.2 |
| VIN_SENSE | U6.1, R9.2 |
| VIN_PROTECTED | U6.9, Q1.3, U7.2, C10.1, R11.1 |
| Q_HS1_GATE | U6.10, Q1.1 |
| MACHINE_POWER_GOOD | U6.8, U7.3, U7.6, R10.2 |
| LM5164_SW | U7.8, L1.1, C11.2 |
| LM5164_BST | U7.7, C11.1 |
| LM5164_RON | U7.4, R11.2 |
| LM5164_FB | U7.5, R12.2, R13.1 |
| RX_5V | L1.2, C12.1, R12.1, R10.1, U5.1, U5.3, C8.1, K1/2/3 pin 5, D1/2/3 cathodes |
| RX_3V3 | U5.5, U2.6, U2.7, C1.1, C2.1, C9.1, U9.13/22/34/44, U10.1, C15/16/17/19 pin1, R16.1, R17.1 |
| CC1354_DCOUPL | U9.23, C18.1 |
| CC1354_RESET_N | U9.35, R16.2 |
| CC1354_VDDR | U9.45, U9.48 |
| MCP_SPI_SCK | U9.12 → exact U10.3 SCK |
| MCP_SPI_CS_N | U9.14, R17.2 → exact U10.2 CS |
| MCP_SPI_MOSI | U9.15 → exact U10.4 SDI |
| MCP_SPI_MISO | U9.16 → exact U10.5 SDO |
| MCP_SHDN_SAFE_N | R18.1 → exact U10.7 SHDN |
| RELAY_K1_DRIVE | U9.26, R19.1 |
| RELAY_K1_GATE | R19.2, Q4.1, R22.1 |
| RELAY_K1_COIL_NEG | Q4.3, D1.2 → exact K1.2 coil |
| RELAY_K2_DRIVE | U9.27, R20.1 |
| RELAY_K2_GATE | R20.2, Q5.1, R23.1 |
| RELAY_K2_COIL_NEG | Q5.3, D2.2 → exact K2.2 coil |
| RELAY_K3_DRIVE | U9.28, R21.1 |
| RELAY_K3_GATE | R21.2, Q6.1, R24.1 |
| RELAY_K3_COIL_NEG | Q6.3, D3.2 → exact K3.2 coil |
| RF915_P_OPEN | U9.3 only |
| RF915_N_OPEN | U9.4 only |
| RF_PA20_P_OPEN | U9.5 only |
| RF_PA20_N_OPEN | U9.6 only |
| LM5069_UVLO_OPEN | U6.3 only |
| LM5069_OVLO_OPEN | U6.4 only |
| LM5069_TIMER_OPEN | U6.6 only |
| LM5069_PWRSET_OPEN | U6.7 only |
Ground Domains
DGND_SERVICE
J1 grounds/shields; U1 pins 3/8; U2 pins 3/29; U6.5; U7.1/EP; U5.2; U9 EP; exact U10.8; C1/C2/C8/C9/C10/C12/C15/C16/C17/C18/C19 returns; R1/R2/R4/R13/R18/R22/R23/R24 returns; Q4/Q5/Q6 sources.
AIRTAG_PACK_NEG
U3 pins 4/5/EP; U8 pins 3/9/EP; C3/C4/C5/C6/C13/C14 returns; R6/R7/R8/R15/R25 returns.
Final Open / DNP Checklist
Table
| Item | State |
|---|---|
| J1 exact JA3 footprint | OPEN — use JAE SJ122206 before PCB |
| Battery MPN/chemistry/capacity | OPEN |
| U8 PS/SYNC | OPEN in current netlist; Phase 2 recommendation is GND/power-save |
| LM5069 UVLO/OVLO/TIMER/PWR | OPEN/TBD |
| U9 RF antenna/matching | OPEN; no antenna |
| U10 V+/V−/P0A/P0B/P0W | OPEN; external analog contract undefined |
| K1/K2/K3 contacts | OPEN external contacts; no loads/machine |
| Q2/Q3 | DNP / BENCH_ONLY / all pins NC |
| U4 COUT/DOUT | OPEN; protection FET implementation absent |
| USB VBUS divider destination | OPEN |
This manifest is sufficient to manually redraw the current shadow architecture in EasyEDA while applying the officially verified corrections for U10, K1–K3 and L1. It is not a fabrication or energization release.
EasyEDA Manual Reconstruction Manifest — Brand NewDay
Critical Reconstruction Rules
Block 1 — USB-C Service / ESD / USB-UART
Component List
Pin-to-Net
J1 — DX07S016JA3R1500 logical mapping
U1 — TPD4E02B04DQAR
U2 — CP2102N-A02-GQFN28
Passives
Block 2 — BQ25185 Charger / Battery Protection / AirTag Buck-Boost
Component List
Pin-to-Net
U3 — BQ25185DLHR
U4 — BQ29700DSER
U8 — TPS63030DSKR
Passives
Battery Decision State
Block 3 — Protected High-Voltage Input / 5 V Buck / 3.3 V LDO
Component List
Pin-to-Net
U6 — LM5069MM-1/NOPB
Q1 — CSD19536KTT
U7 — LM5164DDAR
L1 — MSS1246T-683MLB
U5 — TPS7A2033PDBVR
Passives
Open LM5069 Networks
Block 4 — CC1354P106 Controller / UART / SPI / RF
Component List
U9 Pin-to-Net
Passives
Block 5 — MCP41HV51 Digital Potentiometer
Component List
Official U10 Pin-to-Net for EasyEDA
Support Passives
Block 6 — Three Relay Driver Channels
Exact Relay Specification
Official G5LE-14-DC5 pins
Channel K1
Channel K2
Channel K3
Block 7 — Experimental DNP Paths
Complete Net Membership Summary
Ground Domains
DGND_SERVICE
AIRTAG_PACK_NEG
Final Open / DNP Checklist
