ADC09SJ1300AAVT
Analog to Digital Converters - ADC Single-channel, 9-bit, 1.3-GSPS analog-to-digital converter (ADC) with JESD204C interface 144-FCBGA -40 to 85 ADC09xJ1300 is a family of quad, dual and single channel, 9-bit, 1.3GSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09xJ1300 ideally suited for suited for a variety of multi-channel communications and test systems. Full-power input bandwidth (-3dB) of 6GHz enables direct RF sampling of L-band and S-band. A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltagecontrolled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems. JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes (dual and quad channel devices) or 1 to 4 lanes (for the single channel device), with SerDes baud-rates up to 17.16Gbps, to allow the optimal configuration for each application. Features • ADC Core: – Resolution: 9 Bit – Maximum sampling rate: 1.3GSPS – Non-interleaved architecture – Internal dither reduces high-order harmonics • Performance specifications (–1dBFS): – SNR (100 MHz): 53.5dBFS – ENOB (100 MHz): 8.5 Bits – SFDR (100 MHz): 64dBc – Noise floor (–20dBFS): –143dBFS • Full-scale input voltage: 80 mVPP-DIFF • Full-power input bandwidth: 6GHz • JESD204C Serial data interface: – Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes – Maximum baud-rate: 17.16Gbps – 64B/66B and 8B/10B encoding modes – Subclass-1 support for deterministic latency – Compatible with JESD204B receivers • Optional internal sampling clock generation – Internal PLL and VCO (7.2–8.2GHz) • SYSREF Windowing eases synchronization • Four clock outputs simplify system clocking – Reference clocks for FPGA or adjacent ADC – Reference clock for SerDes transceivers • Timestamp input and output for pulsed systems • Power consumption (1GSPS): – Quad Channel: 450mW / channel – Dual channel: 625mW / channel – Single channel: 940mW • Power supplies: 1.1V, 1.9V #CommonPartsLibrary #IntegratedCircuit #ADC #HighSpeedADC #RFADC #JESD204C #13GSPS #9bitADC #DirectRFSampling #TexasInstruments #MixedSignal #DataAcquisition #JESD204... show more0 Uses
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SMF5.0A-T13
TVS DIODE 5VWM 9.2VC SOD-123FL The SMF series is designed specifically to protect sensitive electronic equipment from voltage transients induced by lightning and other transient voltage events. SMF package is 50% smaller in footprint when compare to SMA package and deliverying one of the low height profiles (1.1mm) in the industry • 200W peak pulsepower capability at 10/1000µs waveform, repetition rate (duty cycle): 0.01% •Compatible with industrial standard package SOD-123FL • Low profile: maximum height of 1.1mm. • Low inductance, excellent clamping capability • For surface mounted applications to optimize board space • High temperature to reflow soldering guaranteed: 260°C/430sec • Typical failure mode is short from over-specified voltage or current • Whisker test is conducted based on JEDEC JESD201A per its table 4a and 4c • IEC-61000-4-2 ESD 30kV(Air), 30kV (Contact) • ESD protection of data lines in accordance with IEC 61000-4-2 • EFT protection of data lines in accordance with IEC 61000-4-4 • Fast response time: typically less than 1.0ns from 0 Volts to VBR min • Glass passivated junction • Built-in strain relief • Plastic package is flammability rated V-0 per UL 94 • Meet MSL level1, per J-STD-020, LF maximun peak of 260°C • Matte tin lead–free plated • Halogen-free and RoHS compliant • Pb-free E3 means 2nd level interconnect is Pb-free and the terminal finish material is tin(Sn) (IPC/ JEDEC J-STD609A.01) • UL Recognized to UL 497B as an Isolated Loop Circuit Protector. #CommonPartsLibrary #Diode... show more45 Uses
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