Power Distribution Network Analysis
0:48
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Table
| Droop Level | Location | L–C Interface | Key Characteristics |
|---|---|---|---|
| Zeroth (On-Die) | Within the silicon | On-die interconnect inductance & embedded capacitance | • Decoupling caps embedded in the die (< nH L, < nF C) |
| • Fastest transient response (ps–ns) | |||
| First (Chip-Package) | Chip package pins and balls | Bond-wire or paddle inductance (~1–5 nH) + package decoupling (1–10 µF) | • Handles die-to-package switching currents |
| • Response in ns–tens of ns | |||
| Second (Package-Board) | PCB land pattern & package footprint | Lead-frame or ball inductance (5–20 nH) + board-side decoupling (10–100 µF) | • Bridges package to board planes |
| • Response in tens–ns to hundreds-ns | |||
| Third (Board-VRM) | VRM output to PCB planes | Bulk inductance of VRM-to-plane path (10–100 nH) + bulk capacitance (100–1000 µF) | • Governs slowest transients (µs–ms) |
| • Sets overall voltage droop under load steps |
Reviews
USB type-C PD DFP [ALT_1_ML1&2PP] [Net Pri Set]
Properties
Pricing & Availability
Distributor | Qty 1 |
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