Power Distribution Network Analysis

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Accessing knowledge base.

Here’s a concise classification of the four PDN-droop levels, each defined by its local L–C interface:

Table


Droop LevelLocationL–C InterfaceKey Characteristics
Zeroth (On-Die)Within the siliconOn-die interconnect inductance & embedded capacitance• Decoupling caps embedded in the die (< nH L, < nF C)
• Fastest transient response (ps–ns)
First (Chip-Package)Chip package pins and ballsBond-wire or paddle inductance (~1–5 nH) + package decoupling (1–10 µF)• Handles die-to-package switching currents
• Response in ns–tens of ns
Second (Package-Board)PCB land pattern & package footprintLead-frame or ball inductance (5–20 nH) + board-side decoupling (10–100 µF)• Bridges package to board planes
• Response in tens–ns to hundreds-ns
Third (Board-VRM)VRM output to PCB planesBulk inductance of VRM-to-plane path (10–100 nH) + bulk capacitance (100–1000 µF)• Governs slowest transients (µs–ms)
• Sets overall voltage droop under load steps
  • Each level “droops” (voltage sags) under fast load steps until the next-closest L–C stage can respond.
  • Proper PDN design ensures enough capacitance at each level so that the switching current is first met by the fastest (lowest-L) stage, then handed off progressively to bulk stages.
  • Tuning L–C values at each interface (e.g., package caps, board ceramic arrays, bulk electrolytics) controls both the magnitude of droop and the transient-recovery time at that hierarchy level.
Package decap selection
Board decap selection
Bulk cap options
PDN impedance analysis
Simulate droop response
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