COM Express NAS Carrier Board Design
1:49
Chat History
Project
Layout
Clarifying component-linking rules.
Structuring the POWER sheet.
Clarifying the POWER sheet details.
Focusing on component linking.
Preparing the POWER sheet output.
Finalizing component linking.
POWER sheet (completed)
Symbols and reference designators (placeholders)
- J_USB_C — USB_C_Receptacle (power-only)
- U_PD — USB_PD_Sink_Controller (EPR capable)
- D_TVS — TVS_Diode on VBUS
- U_HS — Hot_Swap_Controller / eFuse
- U_5V — Buck_5V_12A_Placeholder
- U_3V3 — Buck_3V3_Placeholder
- Option A: U_COMIN — Buck_COMIN_Placeholder (VBUS_HV -> COM_IN)
- Option B: JP_COMIN — COM_IN pass-through (0 Ω link) placeholder (VBUS_HV -> COM_IN)
- TP_BP — Test Point (+5V_BP_SENSE)
- TP_BPG — Test Point (GND_BP_SENSE)
- R_TIE_P — 0 Ω placeholder for +5V_BP_SENSE tie
- R_TIE_G — 0 Ω placeholder for GND_BP_SENSE tie
- X_TIE — CHASSIS_TO_GND_TIE placeholder network
- Generic enable/pull placeholders: R_EN5V, R_EN3V3, R_ENNIC as needed
Hierarchical ports (exact net names)
- Rails/grounds: VBUS_HV, +5V_BACKPLANE, +3V3, COM_IN, +5V_USB, GND, CHASSIS_GND, CHASSIS_TO_GND_TIE
- Control/status: EN_5V_BACKPLANE, EN_3V3, EN_NIC_RAILS, PGOOD_5V, PGOOD_3V3, PGOOD_COMIN, FAULT_PSU, PD_OK, PD_HIGH_POWER_OK, PD_DERATE, +5V_BP_SENSE, GND_BP_SENSE
Power-path wiring (logical)
- J_USB_C.VBUS → D_TVS.A → U_HS.IN
- U_HS.OUT → VBUS_HV (hierarchical port)
- J_USB_C.CC1 ↔ U_PD.CC1 (direct local wire, no global net label)
- J_USB_C.CC2 ↔ U_PD.CC2 (direct local wire, no global net label)
- U_PD status outputs → PD_OK, PD_HIGH_POWER_OK, PD_DERATE (hierarchical ports)
- U_HS.FAULT → FAULT_PSU (hierarchical port)
- J_USB_C.SHELL → CHASSIS_GND
- All device grounds (U_PD, U_HS, U_5V, U_3V3, U_COMIN if used, D_TVS cathode return) → GND
Regulators and rails (star from VBUS_HV)
- VBUS_HV → U_5V.VIN; U_5V.VOUT → +5V_BACKPLANE
- U_5V.EN ← EN_5V_BACKPLANE
- U_5V.PGOOD → PGOOD_5V
- VBUS_HV → U_3V3.VIN; U_3V3.VOUT → +3V3
- U_3V3.EN ← EN_3V3
- U_3V3.PGOOD → PGOOD_3V3
- COM_IN selectable branch (populate only one):
- Option A (buck): VBUS_HV → U_COMIN.VIN; U_COMIN.VOUT → COM_IN; U_COMIN.PGOOD → PGOOD_COMIN
- Option B (pass-through): VBUS_HV → JP_COMIN → COM_IN; PGOOD_COMIN sourced from a generic “COM_IN_GOOD” placeholder on U_COMIN block
- +5V_USB: exposed as a separate rail (hierarchical port), not tied to +5V_BACKPLANE on this sheet
Backplane sense (Rev-A ties)
- +5V_BACKPLANE → R_TIE_P → TP_BP → +5V_BP_SENSE (hierarchical port)
- GND → R_TIE_G → TP_BPG → GND_BP_SENSE (hierarchical port)
Chassis bonding (single point)
- CHASSIS_GND ↔ X_TIE ↔ GND
- Export CHASSIS_TO_GND_TIE (hierarchical port) at X_TIE to indicate intentional single bond location
Notes/constraints applied
- USB-C is power-only; no D+/D- routing on this sheet.
- VBUS chain: USB-C VBUS → TVS → Hot-swap/eFuse → VBUS_HV.
- Star topology: VBUS_HV feeds 5V and 3.3V bucks, and the COM_IN option block.
- +5V_USB is a distinct rail placeholder for rear I/O (USB-A, HDMI_5V_OUT via switch/fuse on REAR_IO), not tied to +5V_BACKPLANE.
- CHASSIS_GND only bonds to GND through X_TIE; no other chassis–digital bonds on this sheet.
- All enable/PGOOD/PD nets are exposed as hierarchical ports; generic resistors provided only as placeholders (no values).
Pull in from project
Library placeholders list
Net name audit
Chassis bond check
20 days
Ready to start.
Show Plan
Reviews
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- 47 kOhms ±5% 0.125W, 1/8W Chip Resistor 0805 (2012 Metric) Automotive AEC-Q200 Thick Film #forLedBlinkjharwinbarrozo1.2M
- 10uF Capacitor Aluminum Polymer 20% 16V SMD 5x5.3mm #forLedBlink #commonpartslibrary #capacitor #aluminumpolymer #radialcanjharwinbarrozo1.2M
- Yellow 595nm LED Indication - Discrete 1.7V 1206 (3216 Metric) #forLedBlinkjharwinbarrozo1.1M
Inspect
Specific Amber Dejarik
Controls
Properties
Rear I/O Order (Target)
HDMI, USB-A x2, 2.5GbE RJ45, 10GbE SFP+, USB-C PD
Board Orientation
Vertical mount on left-chamber dividing wall; rear I/O facing back edge; cutout to right chamber for backplane cables.
Routing Requirements
Controlled impedance for PCIe Gen3, SATA 6G, HDMI TMDS; ground stitching around SFP+ cage; isolate 5V@12A power from high-speed region.
System Architecture
flowchart TD
COM_MOD["COM Express Type 6 Compact"] -->|"PCIe Gen3 x4"| NIC10G["10GbE PCIe Endpoint"]
NIC10G --> SFP["SFP+ Cage"]
COM_MOD -->|"PCIe Gen3 x1"| NIC25G["2.5GbE PCIe NIC"]
NIC25G --> RJ45["RJ45 Magjack"]
COM_MOD -->|"PCIe Gen3 x2"| ASM["ASM1166"]
ASM --> SASA["SFF-8643 Port A SATA0-3"]
ASM --> SASB["SFF-8643 Port B SATA4-5"]
COM_MOD -->|"PCIe Gen3 x1"| M2["M.2 E-key WiFi"]
COM_MOD -->|"USB2"| USBA1["USB-A Port 1"]
COM_MOD -->|"USB2"| USBA2["USB-A Port 2"]
COM_MOD -->|"USB2"| BT["M.2 BT USB2"]
COM_MOD -->|"HDMI"| HDMI["HDMI Connector"]
USBC["USB-C PD In"] --> PD["PD Sink"]
PD --> HOTSWAP["Hot-swap eFuse"]
HOTSWAP --> VBUS_HV["VBUS_HV"]
VBUS_HV --> BUCK5["5V Backplane"]
VBUS_HV --> BUCK33["3V3"]
VBUS_HV --> COMIN["COM_IN"]
VBUS_HV --> NICRAILS["NIC Rails"]
Availability & Pricing
| Distributor | Qty 1 | |
|---|---|---|
Assets
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