Press Brake Control PCB Design

flux

0:00

Work done
  • Implemented the start of an optimized connector pinout by renaming placeholder nets on the field connectors:
    • J2: renamed pins to AO_X_CMD, AO_R_CMD, AI_Y1_SCALE, AI_Y1_RET, AI_Y2_SCALE, AI_Y2_RET.
    • J3: renamed pins to DO_Y1_VALVE, DO_Y2_VALVE, DO_PUMP_VALVE.
  • Verified the existing core digital wiring state for Ethernet RMII and SPI between U11, IC1, J1, U12, and IC6.
Success criteria review
  • ❌ Ethernet RMII/SPI/analog IO/LVDT/ISO1211/valve-driver wiring is not fully completed end-to-end.
  • ❌ Optimized J2/J3 pinout is only partially applied (several intended renames were skipped due to net-name collisions with existing nets).
  • ❌ Support circuits not completed (notably +- analog rails distribution and remaining decoupling/filters/termination).
  • ❌ Metadata normalization via rewrite_component_properties not completed.
  • ❌ ERC/DRC not clean; PCB shows 231 airwire errors (unrouted nets).
  • ❌ Manufacturing exports not generated.
Remaining blocker Net rename collisions prevented applying the complete pinout (e.g., multiple intended pins wanted to become GND, +24V, and DI_Y_LIM, but those net names already exist, so Flux rejected the renames). Until I resolve the connector pin labeling without colliding (either by keeping per-pin nets like J2_2/J2_4 and explicitly connecting them to existing GND/+24V nets, or by using unique net names like GND_AO/GND_AI and then tying to GND), I cannot accurately finish the remaining wiring and documentation.
Next steps I can finish this in the next pass by:
  • Rewiring J2/J3 pins to the already-existing GND, +24V, and DI_Y_LIM nets using rewrite_connections (no renames required).
  • Completing analog IO wiring (DAC -> U21/U22 -> AO_X_CMD/AO_R_CMD, ADC inputs -> AI_Y1_SCALE/AI_Y2_SCALE), three LVDT channels (U13-U15), ISO1211 input conditioning (U23-U32), and valve drivers (U18-U20 with Q1-Q6 and D1-D6).
  • Then normalizing metadata with rewrite_component_properties, re-checking ERC/DRC, and exporting Gerber/ODB++/BOM/pickplace/STEP.
3 days
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    Power Net Portal
    Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power
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  • Generic Capacitor
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Real Tan Sonic Screwdriver thumbnail
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Properties

Pricing & Availability

Distributor

Qty 1

Arrow

$532.84–$703.34

Digi-Key

$158.45–$160.12

LCSC

$761.76

Mouser

$867.39

TME

$41.33

Verical

$538.43–$775.82

Assets

Assets are files uploaded to this project which can be used in various ways.

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