Project Start
Worked for 1 sec
I started the full wiring pass and made real schematic changes, but I’m blocked now because there are no available ACUs, so I can’t continue executing mutations or ERC cleanup.
What was completed:
- Added support passives for USB VBUS, eFuse, AP63203 buck, isolated power filtering, LDOs, MCU decoupling, isolated I2C pull-ups, SRC4392 decoupling, clock decoupling, reset, and AES3 termination.
- Wired USB-C VBUS/GND, USB D+/D− with ESD, CC1/CC2 to TUSB320, TPS25210 eFuse, AP63203 3.3 V buck, and TUSB320 power/config/I2C.
- Datasheet check found an important correction: AP63203 is fixed 3.3 V, so the added FB divider must be removed and FB tied to the 3.3 V output sense.
- Datasheet check also confirmed RT1024 needs internal DCDC support: 4.7 µH inductor, 33 µF output cap, and delayed DCDC_PSWITCH assertion.
Open items:
- Remove AP63203 FB divider R4/R5 and tie U5 FB to 3V3_MCU.
- Change AP63203 inductor L1 from 2.2 µH to 3.9 µH.
- Add/wire RT1024 internal DCDC parts and 24 MHz MCU clock source.
- Finish MCU power/reset/debug, isolation barrier, SRC4392, clocks, AES3 transformer/XLR wiring.
- Run ERC and fix both electrical issues and schematic-wire collision/label cleanup once ACUs are available.
Fix AP63203 first
Manual AP63203 steps
RT1024 DCDC wiring
Check SRC4392 datasheet
Prioritize ERC cleanup
Refine this doc
Ask about this doc
Rev A Component Selection — AES3-USB
Status: Rev A schematic-selection draft
Date: 2026-07-26
Project: AES3-USB
Date: 2026-07-26
Project: AES3-USB
1. Selection Summary
This Rev A selection keeps the frozen architecture:
- USB-C power/data and MIMXRT1024 remain on the USB/UI side.
- SRC4392, AES3 transformers/XLRs, and dual low-jitter oscillators remain on the isolated audio side.
- OLED, LEDs, and UI/prototype I2C remain on the USB/UI side.
- The isolation barrier is crossed only by isolated power and intentional digital isolators.
- No USB Power Delivery; use USB-C 5 V with CC/current-awareness.
Two exact preferred parts are not currently available as verified Flux library parts and need part creation/import before schematic capture:
- NXP MIMXRT1024DAG5A — confirmed real NXP 144-LQFP i.MX RT1024 with 4 MB on-chip flash, but not found as an exact Flux library component.
- Crystek CCHD-957-25-22.5792 — preferred low-jitter 22.5792 MHz companion oscillator exists at distributors, but the exact part was not found in Flux.
Missing-part requests were submitted for both.
2. Primary Rev A Parts
Table
| Block | Selected part | MPN / family | Flux status | Notes |
|---|---|---|---|---|
| MCU | NXP i.MX RT1024 | MIMXRT1024DAG5A | Needs part creation/import | Preferred exact MCU: Cortex-M7, 500 MHz, 4 MB on-chip flash, 144-LQFP. Avoid mandatory external QSPI for Rev A unless firmware needs extra storage. |
| Audio interface / SRC | TI SRC4392 | SRC4392IPFB | Library candidates found | Use TQFP-48. Verify chosen library symbol/footprint against TI datasheet before wiring. |
| USB-C receptacle | GCT USB-C USB 2.0 receptacle | USB4215-03-A or equivalent 16-pin USB-C 2.0 receptacle | Library candidate found | USB 2.0 data + VBUS + CC pins only. |
| USB-C CC/current awareness | TI Type-C CC controller | TUSB320LAIRWBR | Library candidate found | Use sink/UFP behavior to detect advertised Type-C current. No PD contract. |
| USB data ESD | TI low-cap ESD array | TPD4E02B04DQA | Library candidate found | Place adjacent to USB-C connector. |
| VBUS TVS | 5 V unidirectional TVS | SMF5.0A preferred for robust VBUS surge | Library candidate found | Use on 5 V entry; place close to connector/eFuse input. |
| USB input protection | TI eFuse | TPS25210LRPWR | Library candidate found | Set ILIM around the selected USB current policy; recommended starting point about 1 A, not unlimited. |
| USB-side 3.3 V buck | Diodes synchronous buck | AP63203WU-7 | Library candidate found | Active, fixed 3.3 V, 2 A, spread-spectrum. Replaces PAM2305 because PAM2305 fixed variants are not recommended for new designs. |
| Isolated 5 V supply | XP Power isolated DC/DC | ISU0205S05 | Library candidate found | 5 V in, isolated 5 V out, 2 W / 400 mA class. Treat as noisy pre-regulator; add filtering and post-regulators. |
| Audio 3.3 V LDO | MPS low-noise LDO | MP20051DQ-LF-P | Library candidate found | General 3V3_AUDIO_CLEAN post-regulator. Verify output-set network and stability caps. |
| Clock 3.3 V LDO | MPS fixed low-noise LDO | MP20056GJ-33-Z | Library candidate found | Dedicated 3V3_CLK_CLEAN for oscillators and, if quiet enough, clock buffer. Consider premium LT3042/TPS7A/ADM715x class if noise testing requires it. |
| SRC 1.8 V LDO | TI low-noise LDO | TPS79318-EP | Library candidate found | 1.8 V, 200 mA; enough for SRC4392 VDD18 design margin based on ~58 mA high-rate typical. |
| I2C isolation | TI isolated I2C | ISO1541 preferred, ISO1540 alternate | Library candidates found | ISO1541 is preferred if MCU is sole I2C controller and SRC4392 does not require SCL clock stretching across the barrier. Use ISO1540 if bidirectional SCL is required. |
| I2S/SAI isolation | Skyworks/Silicon Labs digital isolators | Si8641BB-B-IS1 + Si8642BB-B-IS1 | Library candidates found | Use only for non-MCLK cross-barrier I2S/control/status. Audio-side remains clock master where possible. |
| 24.576 MHz XO | Crystek low-jitter HCMOS XO | CCHD-957-25-24.576 | Library candidate found | Audio-side oscillator for 48 kHz-family rates. |
| 22.5792 MHz XO | Crystek low-jitter HCMOS XO | CCHD-957-25-22.5792 | Needs part creation/import | Preferred companion oscillator for 44.1 kHz-family rates. Abracon ASELJ-E-22.5792MHZ-L-R-T is a library fallback but not preferred for low-jitter audio. |
| Clock mux/buffer | TI low-jitter clock mux/fanout | CDCLVC1310RHBR | Library candidate found | 25 fs typ additive jitter, but 3:10 is overkill. Tie off/disable unused outputs and revisit if a smaller low-jitter 2:1 mux becomes available. |
| AES3 transformers | Murata digital audio transformer | DA101C | Library candidate found | Use one per AES3 input/output channel. Verify termination topology against SRC4392/AES3 reference circuit. |
| AES3 input XLR | Neutrik female PCB XLR | NC3FAH2 preferred | Library candidate found | Prefer separate shell/ground contact so pin-1/chassis strategy remains explicit. |
| AES3 output XLR | Neutrik male PCB XLR | NC3MAH | Library candidate found | Confirm exact shell/pin-1 behavior during footprint verification. |
| OLED prototype/display | 0.96 in SSD1306 I2C OLED module | Flux OLED 128x64 0.96 in candidate | Library candidate found | Keep on USB/UI I2C and 3V3_USB_MCU only. |
| Status LEDs | 0603 LEDs | Green THG1111C-0005-TR, red 5990010007F or equivalents | Library candidates found | Use low current, nominal 1–2 mA each where possible. |
| Prototype headers | 2.54 mm 1x6 headers | Samtec TSW-106-07-G-S or equivalent | Library candidate found | USB-side header: 5V_PROT, 3V3_USB_MCU, GND, SDA, SCL, spare/reset/UART as selected. |
| Debug connector | ARM SWD 10-pin 1.27 mm | CNC Tech 3220-10-0300-00 or equivalent | Library candidate found | Use full 10-terminal part, verify pinout. |
| Test points | SMT test points | Keystone 5019/5018 or generic test pads | Library candidate found | Put on all rails, MCLK, I2C sides, reset/status, and AES3 bring-up nodes. |
| Reset/boot buttons | SMT tactile switch | Omron B3FS-1002P or XUNPU TS-1088 | Library candidates found | Reset and boot/recovery access. |
3. Power Budget Draft
This budget is intentionally conservative for selecting power-path parts. Exact values must be refined after schematic capture and datasheet pin-mode choices.
Table
| Rail / source | Loads included | Typical planning current | Design allowance | Selection impact |
|---|---|---|---|---|
| 3V3_USB_MCU | MIMXRT1024, USB-side logic, TUSB320, OLED reserve, five low-current LEDs, isolator primary sides, prototype header reserve | ~230 mA | 500 mA | AP63203 2 A buck gives large margin and keeps heat low. |
| 5V_PROT direct / input | eFuse, USB-C controller, isolated DC/DC input, 3.3 V buck input | ~450 mA total typical USB input | ~750–900 mA design case | TPS25210 current limit should start near 1 A unless firmware enforces a lower advertised-current mode. |
| ISO_5V_AUDIO | Input to audio/clock/1.8 V post-regulators and isolator secondary loads | ~180–230 mA | ~300–350 mA | ISU0205S05 2 W / 400 mA output is appropriate but not huge; leave filtering and thermal margin. |
| 3V3_AUDIO_CLEAN | SRC4392 3.3 V rails, audio-side isolator logic, misc audio-side logic | ~90–120 mA | 200 mA | MP20051DQ class 1 A LDO is electrically ample; thermal dissipation remains manageable. |
| 3V3_CLK_CLEAN | Two CCHD-957 oscillators, clock mux/buffer | ~65–90 mA | 150 mA | MP20056 250 mA LDO is adequate; noise and PSRR matter more than current. |
| SRC_1V8 | SRC4392 VDD18/core rail | ~58 mA high-rate typical | 100–150 mA | TPS79318 200 mA is adequate. |
Preliminary USB input expectation: typical operation should fit under about 500 mA if LED current is kept low. Worst-case/full-prototype allowance can approach 750–900 mA, mainly from the isolated converter plus MCU/UI margin. Therefore Rev A should keep TUSB320 current-awareness and firmware/power policy hooks, even though USB PD is intentionally not used.
4. Clocking Decision
Rev A clock policy:
- Both audio oscillators are born on the isolated audio side.
- Both oscillators remain continuously powered/running.
- The selected oscillator output is muxed/buffered locally on the audio side.
- MCLK must not cross the isolation barrier through a generic digital isolator.
- If I2S/SAI crosses the barrier, the audio side should be clock master where feasible; only data and non-jitter-critical clocks/status cross through Si864x isolators.
The CDCLVC1310 is accepted as the current Flux-available mux/buffer because its datasheet reports very low additive jitter, but it is over-sized. During schematic capture, disable unused outputs and keep its rail/return/layout tightly controlled. If a smaller low-jitter 2:1 LVCMOS mux becomes available, it should replace CDCLVC1310 before layout.
5. Isolation and Noise Notes
- The isolated DC/DC is not a clean audio supply by itself; it is only an isolated pre-regulator.
- Add USB-side input filtering before the isolated converter.
- Add isolated-side π/ferrite filtering and damping before audio/clock LDOs.
- Keep USB_GND and ISO_GND_AUDIO separated except through intentional safety/EMC/chassis elements.
- ESD return paths for USB shell, XLR shell/pin-1, and AES3 line protection must not accidentally defeat galvanic isolation.
- OLED and LEDs must remain on 3V3_USB_MCU; no OLED/LED current on 3V3_AUDIO_CLEAN or 3V3_CLK_CLEAN.
6. Open Verification Items Before Schematic Capture
- Create/import exact MIMXRT1024DAG5A Flux part and verify NXP reference pinout, power pins, reset/boot pins, and USB routing requirements.
- Create/import exact CCHD-957-25-22.5792 Flux part or accept the Abracon fallback with explicit jitter-performance downgrade.
- Confirm exact number of AES3 inputs and outputs; the current default assumes one AES3 input and one AES3 output.
- Verify SRC4392 supply sequencing, reset, decoupling, and recommended AES3 input/output circuits from TI datasheet.
- Verify Si864x I2S timing against selected SAI mode: BCLK rate, LRCLK, setup/hold, channel skew, and direction allocation.
- Verify ISO1541 vs ISO1540 choice after confirming whether SRC4392 can ever stretch SCL.
- Confirm final USB-C current policy: default-current-safe mode vs 1.5 A-capable behavior when advertised by the source.
- Select exact passive values for AP63203, TPS25210, LDOs, filters, AES3 termination, LED resistors, and I2C pull-ups during schematic capture from datasheets.
- Confirm enclosure/chassis/pin-1/shield plan before layout.
- Consider swapping CDCLVC1310 to a smaller low-jitter 2:1 clock mux if a verified part becomes available.
1. Selection Summary
2. Primary Rev A Parts
3. Power Budget Draft
4. Clocking Decision
5. Isolation and Noise Notes
6. Open Verification Items Before Schematic Capture
