• TI SRC4392 as the AES3 receiver/transmitter and sample-rate conversion / digital audio interface device.
• NXP MIMXRT1024 as the USB-side MCU for USB connection, configuration/control, firmware, UI, and digital audio interface logic.
• I2S/SAI and I2C between the MCU domain and SRC4392 domain, with galvanic isolation between USB/UI and audio/AES3.
• AES3 input and output on XLR connectors.
• Low-jitter standard-frequency audio MCLK generated on the isolated audio side.
• USB-C 5 V bus power only, no USB Power Delivery.

Diagram

• USB_5V_RAW: VBUS directly after USB-C connector protection entry. Use only for input protection, detection, and upstream power conversion.
• 5V_PROT: protected/filtered 5 V system rail after fuse/current limit and EMI filtering. Expose this rail on a prototype header.
• 3V3_USB_MCU: main USB-side 3.3 V rail for MIMXRT1024 I/O domains, QSPI flash if 3.3 V, USB-side logic, OLED, LEDs, and UI/prototype I2C pull-ups.

• ISO_5V_AUDIO: isolated 5 V generated from USB 5 V by an isolated DC/DC converter.
• 3V3_AUDIO_CLEAN: low-noise post-regulated isolated 3.3 V for SRC4392 audio-side digital/interface logic and any clean audio-side support logic.
• 3V3_CLK_CLEAN: dedicated low-noise regulator/filter for the dual oscillator/MCLK circuitry only. If the selected oscillators warrant separate filtering, split locally into per-oscillator filtered branches.
• SRC4392 1.8 V rail: provide the SRC4392-required 1.8 V rail from the isolated audio side if required by the selected SRC4392 supply scheme.

• Treat the isolation barrier as a board-planning constraint, not a late schematic add-on.
• Keep USB_GND / MCU_GND and ISO_GND_AUDIO as separate domains across the barrier.
• Cross the barrier only through selected isolators and the isolated DC/DC converter.
• Isolate control and digital audio paths required between MIMXRT1024 and SRC4392:
  • I2C SCL/SDA for SRC4392 control.
  • I2S/SAI signals as required: BCLK, LRCLK/FS, SDIN, SDOUT, and any non-jitter-critical control/status lines.
  • Reset/interrupt/status lines as needed.
• Avoid routing a jitter-critical MCLK from the MCU side through a generic digital isolator. Preferred: oscillator and primary MCLK distribution stay on isolated audio side.
• If the MCU requires an audio clock reference, use an isolation strategy intentionally selected for jitter/skew performance, or design the MIMXRT1024 SAI role so the audio side remains clock master.

• Oscillator phase noise is a supply and layout problem; do not power audio oscillators from noisy digital rails.
• Each audio oscillator gets a dedicated low-noise rail or equivalent isolated/filter chain.
• Keep oscillators continuously running; switch only outputs if multiple clock families are used.
• Any clock mux/buffer must be jitter-neutral enough for audio use and glitch-safe for the intended switchover sequence.
• MCLK must be short, impedance-controlled, terminated as needed, stub-free, and routed over an uninterrupted reference plane.
• Keep MCLK separated from USB, AES3 front ends, QSPI/FlexSPI, switchers, and LED/UI routing.
• Define clock mastership per operating mode before final schematic capture.

• Populate 24.576 MHz low-jitter oscillator for 48/96/192 kHz-family rates.
• Populate 22.5792 MHz low-jitter oscillator for 44.1/88.2/176.4 kHz-family rates.
• Keep both oscillators running continuously and switch/select only the oscillator outputs.
• Include a jitter-conscious, glitch-safe clock mux/buffer or equivalent clock-selection circuit from the beginning.
• Make SRC4392/audio side the clock authority where possible; MCU SAI should adapt/slave where feasible.

• AES3 inputs and outputs use XLR connectors.
• Use AES3 transformers selected by bandwidth, pulse fidelity, and low stray/interwinding capacitance, not just nominal 110 Ω compatibility.
• Decide and document whether AES3 termination is on transformer primary or secondary.
• Use low-capacitance ESD protection near connectors.
• Maintain 110 Ω differential impedance where applicable from connector/front-end through transformer/interface path.
• Control AES3 output edge rate for EMC without closing the eye.
• XLR pin 1 / shield bonding is a chassis/panel decision; do not route shield current through the noisy PCB digital ground.
• Plan loopback test path/method from AES3 output to AES3 input.

• Follow the NXP MIMXRT1024 reference design and hardware design guide for USB HS, reset, boot straps, power, decoupling, oscillator/crystal, debug, and external memory.
• Do not reinterpret NXP reference power/reset/boot circuitry casually.
• Use MIMXRT1024DAG5A as the preferred Rev A MCU target: 144-pin LQFP, Cortex-M7 up to 500 MHz, with 4 MB on-chip flash. External QSPI boot memory is not mandatory for Rev A unless firmware/storage requirements later demand it; optional memory pads may be added only if they do not compromise USB/clock/layout priorities.
• Keep QSPI/FlexSPI and other fast MCU buses away from clocks and clean audio circuitry.
• Provide debug/programming access and a recovery path.
• Define pin-mux before schematic capture for USB, I2S/SAI, I2C, reset, boot pins, debug, LEDs, OLED, and prototype headers.

• 5V_PROT
• 3V3_USB_MCU
• USB_GND
• I2C_SCL_UI
• I2C_SDA_UI

• RESET
• one or two spare GPIOs
• UART TX/RX for debug
• boot/recovery strap access if safe

• ISO_5V_AUDIO
• 3V3_AUDIO_CLEAN
• ISO_GND_AUDIO
• isolated/audio-side I2C SCL/SDA if used
• SRC4392 reset/interrupt/status

• OLED and LEDs must remain on the USB/MCU side.
• LED current should be deliberately limited; use high-efficiency LEDs and low currents where possible.
• OLED/I2C pull-ups belong to 3V3_USB_MCU unless using a dedicated isolated I2C channel.
• Do not connect OLED/LED rails to 3V3_AUDIO_CLEAN or 3V3_CLK_CLEAN.

• Minimum recommended PCB: 4-layer with continuous reference planes.
• Use placement separation rather than ground-plane slots.
• Define two main physical zones:
  1. USB/MCU/UI dirty side.
  2. Isolated audio/AES3/clock clean side.
• Keep the isolation barrier clear with creepage/clearance appropriate for selected isolation parts and product goals.
• Place USB-C, USB ESD, and MCU USB pins close with controlled-impedance USB routing.
• Place AES3 XLR connectors at the board edge with transformers/ESD/front-end close and symmetric.
• Place oscillators away from connectors, mounting holes, airflow, heat sources, switchers, QSPI, USB, LEDs, and AES3 edges.
• Keep MCLK path short, stub-free, and over continuous reference.
• Keep isolated DC/DC physically away from oscillator and AES3 receive front end; filter before clean rails.
• Put test points on all major rails and critical clocks/signals.

• USB_5V_RAW / 5V_PROT
• 3V3_USB_MCU
• ISO_5V_AUDIO
• 3V3_AUDIO_CLEAN
• 3V3_CLK_CLEAN
• SRC4392 1.8 V rail if used
• Audio MCLK
• BCLK / LRCLK / I2S data lines as practical
• I2C both sides of isolator
• SRC4392 reset/interrupt/lock/status
• AES3 output waveform
• AES3 input receiver lock

1. USB-C power entry and current draw.
2. USB-side 3.3 V and MCU boot/debug.
3. OLED/LED/UI loads without audio-side power enabled if possible.
4. Isolated DC/DC output and post-regulators.
5. Audio oscillator rail noise and MCLK quality.
6. SRC4392 reset/configuration over isolated I2C.
7. I2S/SAI communication across isolation.
8. AES3 input lock.
9. AES3 output waveform.
10. Hardware loopback.

1. Create/import exact Flux library parts for MIMXRT1024DAG5A and CCHD-957-25-22.5792, or approve alternates.
2. Confirm exact number of AES3 XLR inputs and outputs; current component-selection default is one input and one output.
3. Verify isolated DC/DC noise, isolation capacitance, filtering, and creepage target for ISU0205S05 or any alternate.
4. Verify Si864x I2S/SAI timing/skew against the selected SRC4392/MIMXRT1024 clock-master mode.
5. Keep MCLK local to SRC4392/audio side; do not cross MCLK through a generic isolator unless a separate jitter/timing analysis approves it.
6. Finalize AES3 termination topology around DA101C transformers.
7. Refine the power budget from final datasheet values and selected LED/OLED behavior.
8. Confirm whether final firmware needs USB Audio Class streaming or only USB control/debug initially.
9. Finalize grounding/chassis/shield concept for USB shell and XLR pin 1.
10. Consider replacing CDCLVC1310 with a smaller low-jitter 2:1 clock mux if a verified part becomes available.