Project Start
Worked for 1 sec
I started the full wiring pass and made real schematic changes, but I’m blocked now because there are no available ACUs, so I can’t continue executing mutations or ERC cleanup.
What was completed:
- Added support passives for USB VBUS, eFuse, AP63203 buck, isolated power filtering, LDOs, MCU decoupling, isolated I2C pull-ups, SRC4392 decoupling, clock decoupling, reset, and AES3 termination.
- Wired USB-C VBUS/GND, USB D+/D− with ESD, CC1/CC2 to TUSB320, TPS25210 eFuse, AP63203 3.3 V buck, and TUSB320 power/config/I2C.
- Datasheet check found an important correction: AP63203 is fixed 3.3 V, so the added FB divider must be removed and FB tied to the 3.3 V output sense.
- Datasheet check also confirmed RT1024 needs internal DCDC support: 4.7 µH inductor, 33 µF output cap, and delayed DCDC_PSWITCH assertion.
Open items:
- Remove AP63203 FB divider R4/R5 and tie U5 FB to 3V3_MCU.
- Change AP63203 inductor L1 from 2.2 µH to 3.9 µH.
- Add/wire RT1024 internal DCDC parts and 24 MHz MCU clock source.
- Finish MCU power/reset/debug, isolation barrier, SRC4392, clocks, AES3 transformer/XLR wiring.
- Run ERC and fix both electrical issues and schematic-wire collision/label cleanup once ACUs are available.
Fix AP63203 first
Manual AP63203 steps
RT1024 DCDC wiring
Check SRC4392 datasheet
Prioritize ERC cleanup
Refine this doc
Ask about this doc
PCB Design Handover — AES3-USB
Status: Rev A component-selection draft complete; ready for part creation/import and schematic planning
Design Intent
Build a first prototype that proves the TI SRC4392 and NXP MIMXRT1024 can operate together as a USB-powered, galvanically isolated AES3 interface. Prioritize clock integrity, clean isolated audio power, bring-up access, and clear separation between noisy USB/UI circuitry and the SRC4392/AES3 side.
Frozen Architecture
- USB-C provides 5 V power and USB data. No USB Power Delivery.
- MIMXRT1024 lives on the USB/host side with USB-C, QSPI/boot memory, OLED, LEDs, and UI/prototype I2C.
- SRC4392, AES3 transformers, XLR front ends, and mandatory dual low-jitter audio MCLK oscillators live on the isolated audio side.
- Use an isolated DC/DC converter plus audio-side post-regulators.
- Cross the isolation barrier with selected digital isolators for I2C, I2S/SAI, reset/status, and any required control lines.
- Keep the clean audio MCLK generated on the isolated audio side; avoid sending jitter-critical MCLK through generic digital isolation.
Required Functional Blocks
-
USB-C power/data entry
- USB-C receptacle
- CC sink resistors / current-awareness strategy
- USB ESD near connector
- VBUS TVS/protection
- fuse/current limit
- EMI filtering
-
USB-side MCU domain
- MIMXRT1024
- required external memory / boot support per NXP reference
- debug/programming header
- reset/boot strap access
- USB-side 3.3 V regulator
- OLED/I2C and LED support
- prototype header with 5 V, 3.3 V, GND, I2C
-
Isolation barrier
- isolated DC/DC from USB 5 V to audio side
- digital isolator(s) for I2C and I2S/SAI/control
- clear ground split only across isolation barrier, not by cutting up local return planes inside a domain
-
Audio-side power
- ISO_5V_AUDIO
- 3V3_AUDIO_CLEAN
- 3V3_CLK_CLEAN dedicated oscillator rail
- SRC4392 1.8 V rail if required
- filtering/post-regulation so USB 5 V noise does not reach clock-relevant rails
-
Clocking
- isolated-side low-jitter 24.576 MHz oscillator for 48 kHz-family rates
- isolated-side low-jitter 22.5792 MHz oscillator for 44.1 kHz-family rates
- both oscillators populated and continuously running from Rev A
- low-jitter, glitch-safe mux/buffer or equivalent clock-selection circuit
- MCLK test point and short controlled route to SRC4392
-
SRC4392 + AES3
- SRC4392 with isolated I2C control and I2S/SAI connection to MCU side through isolators
- XLR AES3 input(s) with transformer, termination, ESD, and controlled/symmetric routing
- XLR AES3 output(s) with transformer, output network, ESD, and edge-rate/EMC awareness
- lock/status and reset test access
Power Nets to Name Deliberately
- USB_5V_RAW
- 5V_PROT
- 3V3_USB_MCU
- USB_GND
- ISO_5V_AUDIO
- 3V3_AUDIO_CLEAN
- 3V3_CLK_CLEAN
- ISO_GND_AUDIO
- SRC_1V8 if required
Do not tie USB_GND and ISO_GND_AUDIO together except through intentional isolation/chassis/EMC components if the final grounding concept explicitly requires it.
Prototype Headers
USB-side header, minimum:
- 5V_PROT
- 3V3_USB_MCU
- USB_GND
- I2C_SCL_UI
- I2C_SDA_UI
Recommended extra USB-side header pins:
- UART TX/RX
- RESET
- spare GPIO
- BOOT/recovery access if safe
Optional audio-side service header:
- ISO_5V_AUDIO
- 3V3_AUDIO_CLEAN
- ISO_GND_AUDIO
- isolated I2C SCL/SDA
- SRC reset/interrupt/status
Layout Priorities
- Define isolation barrier and connector edges first.
- Place USB-C, protection, and MIMXRT1024 USB pins for short USB routing.
- Place SRC4392, oscillators, and AES3 front ends on clean isolated side.
- Keep isolated DC/DC physically away from oscillators and AES3 receive path.
- Keep OLED/LED/I2C headers away from audio-side clock and AES3 routing.
- Use continuous ground/reference planes within each side; avoid arbitrary ground slots.
- Keep MCLK short, stub-free, controlled, and away from USB/QSPI/switchers/LEDs.
- Route QSPI/FlexSPI short and keep it away from clocks and audio front end.
- Put ESD devices close to external connectors.
- Provide test points before layout gets dense.
Must-Verify Before Schematic Capture
Current selected parts and rationale are captured in Rev A Component Selection.
- Exact MIMXRT1024DAG5A Flux part creation/import and NXP reference design requirements.
- SRC4392 supply sequencing and reset requirements.
- Digital isolator timing for I2S/SAI speed and skew.
- Enforce that MCLK stays on the audio side unless a separate jitter/timing analysis approves crossing the barrier.
- ISU0205S05 isolated DC/DC current, noise, isolation rating, and filtering.
- DA101C AES3 transformer termination topology.
- Exact number and gender/orientation of XLR inputs/outputs.
- USB current budget including OLED and LEDs.
- Exact CCHD-957-25-22.5792 Flux part creation/import or approved fallback oscillator.
Suggested PCB Designer Stop Points
- Floorplan review: connectors, isolation barrier, major ICs, oscillators, isolated DC/DC.
- Power tree review: rail names, regulators, filtering, test points.
- Clocking review: dual oscillator selection, MCLK ownership, buffer/mux, output switching, supply filtering, and route constraints.
- Isolation review: digital isolator selection and signal directions.
- Final schematic ERC review before placement.
- Placement review before routing.
- Controlled-impedance/high-speed review before manufacturing export.
Design Intent
Frozen Architecture
Required Functional Blocks
Power Nets to Name Deliberately
Prototype Headers
Layout Priorities
Must-Verify Before Schematic Capture
Suggested PCB Designer Stop Points
