Wi-Fi and Bluetooth Sensor Node Design
0:25
I can’t draw the schematic as an image here, but I’ll describe the exact wiring so you can verify it in your schematic and route it on the PCB. Designators below match your project.
Power and decoupling
- Supply:
- Decoupling at U1:
Signal source and mid-bias
- Sensor output:
- J1 Pin_1 (ACS712 module S) → net FILTER_IN.
- Mid-bias:
- R1 and R2 form a divider to create 2.5 V mid-bias from 5 V if needed, but because the ACS712 output is already mid-biased at 2.5 V, tie:
- U1 non-inverting input reference to the same bias node coming from the sensor. In your project this is net MID_BIAS:
- If you keep R1/R2, connect them to make MID_BIAS = 2.5 V: R1:P2 → MID_BIAS, R2:P1 → MID_BIAS, with R1:P1 → VDD and R2:P2 → GND. Otherwise, you can omit R1/R2 and rely on the ACS712 mid-bias.
- R1 and R2 form a divider to create 2.5 V mid-bias from 5 V if needed, but because the ACS712 output is already mid-biased at 2.5 V, tie:
Sallen-Key low-pass filter (unity gain, Butterworth, fc ≈ 100 Hz)
- Values:
- Wiring (non-inverting Sallen-Key):
- Input:
- FILTER_IN → U1 VINA+ (non-inverting input).
- Feedback path:
- U1 VOUTA → R4:P2 and C4:P2.
- R4:P1 → SK_NODE.
- C4:P1 → ADC_IN (or the same output node if you prefer the classic node, see below).
- Feed-forward network:
- R3:P1 → FILTER_IN.
- R3:P2 → SK_NODE.
- C3:P1 → SK_NODE.
- C3:P2 → MID_BIAS (same 2.5 V bias node tied to U1 VINA-).
- Output:
- Node ADC_IN is the filtered output. In your current netlist, ADC_IN connects to U1:VOUTA via R5 and to J2/TP1 as the output node. If you want the classic unity-gain SK wiring, take ADC_IN directly from U1:VOUTA; using the added series/output RC is also fine (see next).
- Input:
ADC interface and anti-aliasing
- Output isolation and RC:
- Optional added series resistor R6 100 Ω was listed; if present, place it either instead of R5 or omit one to avoid doubling the output resistance.
Unused op-amp section
Test pads and output pads
Quick placement guidance for low noise on PCB
- Place R3, R4, C3, C4 clustered around U1A so the loop U1:VOUTA → R4/C4 → SK_NODE → R3/C3 → U1:VINA+ is tight and short.
- Keep C2 0.1 µF right next to U1 VDD to GND; via to the L2 GND plane from the GND pad of C2.
- Keep ADC_IN trace away from board edges and digital lines; place C5 right at TP1/ADC_IN to GND with a short return to the ground plane.
If you want, I can produce a compact step-by-step checklist to place and route these exact nets on the PCB canvas next.
161 days
0:14
Do you mean “PLC” as in Programmable Logic Controller, or are you asking about a signal/net labeled “PLC_IN” on a schematic?
-
PLC (Programmable Logic Controller): An industrial control computer used for automation. “PLC IN” on a device or connector usually means an input signal meant to be read by a PLC (e.g., 24 V digital input, 0–10 V analog input, 4–20 mA current loop), depending on the system.
-
PLC_IN as a net label: It typically denotes a signal coming from, or intended for, a PLC into your board. The electrical levels and interface depend on the context:
- Digital 24 V inputs to PLCs often require an interface module or opto-isolation if you’re connecting from low-voltage electronics.
- Analog PLC inputs can be 0–10 V, ±10 V, 0–5 V, 4–20 mA; you’d need appropriate scaling/filtering.
If you can share where you saw “PLC In” (device, schematic reference, voltage levels), I can tell you exactly what it expects and how to interface it safely.
Clarify context of PLC In label
Ask about PLC input protection
Ask about analog PLC input
Ask about labeling conventions
Ask about interfacing low-voltage logic to PLC
161 days
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