Stereo DSP Amplifier
Worked for 13 mins 30 sec
I’m blocked because your account has no available ACUs, so AI execution tools are unavailable and I can’t continue routing or running final checks right now.
Accomplished so far:
- Applied the uploaded BOM MPNs/footprint fields to the project properties as provided.
- Changed the PCB from 200 × 200 mm to 100 × 100 mm, 4-layer stackup with Layer 2 as ground and Layer 3 as power.
- Re-placed all 141 components on the 100 × 100 mm board with functional separation: analog inputs left, ESP32 top edge, Class-D/output stage right, power/regulators bottom/right.
- Placement is mostly cleaned up, but 3 decoupling-loop warnings remained after the last placement pass: C14, C26, C33.
Open items:
- Route every net.
- Resolve remaining placement/DRC warnings.
- Run final ERC/DRC.
- Confirm whether the custom footprint names from the spreadsheet are accepted by manufacturing/export, since some were set exactly but reported as non-standard property values.
Suggested next steps once ACUs are available:
- Fix C14/C26/C33 placement warnings.
- Run pre-route board check.
- Auto-route the board.
- Run final ERC/DRC and clean remaining issues.
Fix capacitor placement
Check footprint exports
Manual capacitor help
Check board boundary
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Project Specification — Stereo DSP Amplifier
Project Overview
Status: Draft schematic phase. Design a 150 mm × 150 mm four-layer stereo DSP amplifier PCB using the specified signal chain and no major-component substitutions.
Intended Use
Prototype/validation audio amplifier board for balanced stereo inputs, ESP32-S3 real-time DSP, and 4 Ω speaker outputs. Initial operation may use an 18 V / 2 A adapter; power path should support a future 18 V / 5 A adapter.
What the Device Should Do
- Accept two mono balanced 6.35 mm TRS line inputs.
- Convert analog audio to 24-bit / 48 kHz digital audio.
- Keep ESP32-S3 permanently in the I²S audio path for EQ, filters, delay, gain/mute, limiter, presets, Wi-Fi control, ADC/amp I²C setup, and fault monitoring.
- Drive stereo 4 Ω speakers through a TAS5825M Class-D amplifier.
Main Features
- Balanced TRS Left/Right inputs with ESD, RF filtering, AC coupling, and selectable 0 dB / −10 dB / −18 dB pad.
- INA1650IPWR balanced receiver.
- PCM1863DBT stereo ADC.
- ESP32-S3-WROOM-1-N16R8 module.
- TAS5825MRHBR Class-D amplifier.
- 18 V input protection, regulator rails, bulk capacitance, and test points.
System Architecture
Diagram
Hardware Subsystems
- Analog input: two balanced TRS inputs, chassis/shield handling, low-capacitance ESD, symmetrical RF filters, AC coupling, selectable attenuation pad.
- ADC/DSP: PCM1863 receives INA1650 outputs; ESP32-S3 is I²S master at BCLK 3.072 MHz and LRCLK 48 kHz.
- Power amplifier: TAS5825M powered from 18 V PVDD with output filters and speaker terminal blocks.
- Power: 18 V protected input, direct PVDD branch, regulated rails for analog, digital audio, ESP32, and amplifier digital supply.
- Debug/test: test points for every rail, BCLK, LRCLK, ADC DOUT, amp SDIN, I²C, RESET, and FAULT.
Interfaces and Connections
- Audio in: J1/J2 6.35 mm TRS; Tip=Hot+, Ring=Cold−, Sleeve=chassis/shield.
- Speaker out: J4/J5 KF301-2P, 5.08 mm pitch.
- Power in: J3 5.5 × 2.1 mm DC barrel jack, 18 V DC.
- Digital audio: 48 kHz, 24-bit, 32-bit slot I²S; ESP32-S3 as clock master.
- Control: I²C from ESP32-S3 to PCM1863 and TAS5825M; amplifier FAULT to ESP32-S3.
Power and Runtime Expectations
- Input: 18 V DC.
- TAS5825M PVDD powered directly from protected 18 V.
- Initial 18 V / 2 A adapter is not expected to provide continuous 30 W + 30 W output.
- Future power path target: 18 V / 5 A adapter capability.
Power Tree and Power Budget
Preliminary budget to be refined from datasheets during schematic entry:
- 18V_IN_PROTECTED → TAS5825M PVDD, high-current path sized for 5 A.
- 18V_IN_PROTECTED → buck/regulator rails for 5 V/3.3 V domains as required.
- 3V3 expected loads include ESP32-S3 module, PCM1863 digital, TAS5825M digital/control, I²C pull-ups, and test/debug.
- Analog audio rails for INA1650/PCM1863 analog supply will use low-noise regulation/filtering.
Diagram
Manufacturing and Assembly Expectations
- PCB: 150 mm × 150 mm, four layers.
- Layer 2 must be a continuous ground plane.
- Use official manufacturer-recommended land patterns for all ICs.
- Do not perform PCB placement or routing until requested.
Firmware-Relevant Hardware Requirements
- ESP32-S3 must implement DSP audio path, presets, Wi-Fi control, I²C configuration, FAULT monitoring, RESET handling, mute/gain, limiter, and delay.
- Provide stable boot/reset strapping and programming/debug access.
Physical Design Expectations
- ESP32 antenna at PCB edge with official keepout.
- INA1650 close to TRS connectors.
- Keep analog input/ADC away from amplifier switching nodes, output inductors, and DC/DC converters.
- TAS5825M close to output filters and speaker connectors.
Important Design Decisions
- Major signal-chain components are fixed by user requirement and must not be substituted.
- ESP32-S3 is the I²S clock master.
- Add 22–33 Ω source-series resistors on BCLK, LRCLK, ADC DOUT, and amplifier SDIN.
- Schematic and BOM only in this phase; no placement/routing.
Assumptions
- Support passives, protection parts, regulators, buttons, headers, and test points may be selected as needed.
- Exact connector alternatives may be used only where the user explicitly allowed “or equivalent.”
- Final output-filter values and regulator part choices must be verified against datasheets/reference designs.
Change Notes
- Initial specification created from the pasted requirements on 2026-07-25.
Project Overview
Intended Use
What the Device Should Do
Main Features
System Architecture
Hardware Subsystems
Interfaces and Connections
Power and Runtime Expectations
Power Tree and Power Budget
Manufacturing and Assembly Expectations
Firmware-Relevant Hardware Requirements
Physical Design Expectations
Important Design Decisions
Assumptions
Change Notes
