Stereo DSP Amplifier
Worked for 13 mins 30 sec
I’m blocked because your account has no available ACUs, so AI execution tools are unavailable and I can’t continue routing or running final checks right now.
Accomplished so far:
- Applied the uploaded BOM MPNs/footprint fields to the project properties as provided.
- Changed the PCB from 200 × 200 mm to 100 × 100 mm, 4-layer stackup with Layer 2 as ground and Layer 3 as power.
- Re-placed all 141 components on the 100 × 100 mm board with functional separation: analog inputs left, ESP32 top edge, Class-D/output stage right, power/regulators bottom/right.
- Placement is mostly cleaned up, but 3 decoupling-loop warnings remained after the last placement pass: C14, C26, C33.
Open items:
- Route every net.
- Resolve remaining placement/DRC warnings.
- Run final ERC/DRC.
- Confirm whether the custom footprint names from the spreadsheet are accepted by manufacturing/export, since some were set exactly but reported as non-standard property values.
Suggested next steps once ACUs are available:
- Fix C14/C26/C33 placement warnings.
- Run pre-route board check.
- Auto-route the board.
- Run final ERC/DRC and clean remaining issues.
Fix capacitor placement
Check footprint exports
Manual capacitor help
Check board boundary
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Board Bring-Up Plan — Stereo DSP Amplifier
Prerequisites
- Current-limited bench supply capable of 18 V.
- Multimeter, oscilloscope, audio source, 4 Ω dummy loads/speakers, UART/USB-serial adapter if using J6.
- Start with no speakers connected; use dummy loads only after power rails and firmware are verified.
1. Visual Inspection
- Confirm U1 INA1650IPWR, U2 PCM1863DBT, U3 ESP32-S3-WROOM-1-N16R8, U4 TAS5825MRHBR orientation.
- Inspect U4 exposed pad soldering and output filter inductors/caps.
- Verify attenuation jumpers J7–J10 are installed consistently: pin 1 to pin 2 for 0dB, pin 1 to pin 3 for -10dB, or pin 1 to pin 4 for -18dB.
- Confirm BTL speaker terminals are not tied to ground.
2. Power Rail Verification
Table
| Rail | Source | Expected | Measure At | Initial Current Limit | Pass Criteria |
|---|---|---|---|---|---|
| 18V_RAW | J3 | 18 V | TP1 | 100 mA no-load | Within supply setting, no heating. |
| 18V_PROTECTED/PVDD_18V | F1/Q1/D1 | ~18 V | TP2/TP3 | 100 mA no-load | <0.2 V drop at no load. |
| 3V3 | U5 TPS54302 | 3.3 V | TP4 | 300 mA first power | 3.14–3.47 V. |
| ADC_AVDD_3V3 | FB1 from 3V3 | ~3.3 V | TP6 | included above | Within 100 mV of 3V3 at idle. |
| 12V_A | U6 TPS7A4901 | 12 V | TP5 | 50 mA | 11.6–12.4 V. |
Procedure:
- With power off, measure resistance from each rail to GND.
- Apply 18 V with 100 mA limit and verify TP1/TP2/TP3.
- Increase current limit to 300 mA and verify TP4/TP6/TP5.
- Check U5 switching ripple on TP4 and U6 noise/ripple on TP5.
- Only after rails pass, connect programming/debug interface and flash firmware.
3. Critical Signals
Table
| Signal | Net | Expected | Measure At |
|---|---|---|---|
| Reset | ESP_EN_RESET | High after power-up; low when SW1 pressed | TP13 |
| Boot | ESP_BOOT | High normally; low when SW2 pressed | J6 pin 6 / U3 IO0 |
| I2S BCLK | I2S_BCLK | 3.072 MHz when firmware running | TP7 |
| I2S LRCLK | I2S_LRCLK | 48 kHz when firmware running | TP8 |
| ADC data | ADC_DOUT | 3.3 V CMOS data | TP9 |
| Amp data | AMP_SDIN | 3.3 V CMOS data | TP10 |
| I2C SDA/SCL | I2C_SDA/I2C_SCL | 3.3 V idle high, transactions at boot | TP11/TP12 |
| Fault | AMP_FAULT | High normally, low on TAS fault | TP14 |
4. Connector Tests
Table
| Connector | Function | Test |
|---|---|---|
| J1/J2 | Balanced TRS inputs | Verify Tip=hot, Ring=cold, Sleeve=CHASSIS_SHIELD. |
| J3 | 18 V DC input | Verify center-positive assumption before powering. |
| J4/J5 | BTL speaker outputs | Confirm neither pin has continuity to GND. |
| J6 | ESP32 debug/programming | Verify 3V3/GND/UART/BOOT/RESET continuity. |
| J7–J10 | Input pad selection | Verify only one shunt position per leg. |
5. Programming
- Use BOOT SW2 and RESET SW1 to enter ESP32-S3 bootloader when needed.
- Build/flash using the Firmware Starter project file.
- Confirm serial boot log at 115200 baud.
- Verify I2C device detection for PCM1863 and TAS5825M before enabling amplifier output.
6. Functional Validation
Table
| Test | Expected Result |
|---|---|
| I2C scan | PCM1863 and TAS5825M respond at expected addresses. |
| I2S clocks | TP7 = 3.072 MHz, TP8 = 48 kHz. |
| ADC input | Inject low-level sine into J1/J2; observe non-clipped ADC samples in firmware. |
| Amplifier muted boot | U4 stays disabled/muted until firmware configuration completes. |
| Speaker output | With dummy load, observe clean differential output before using speakers. |
| Fault path | Trigger/observe TAS fault state and confirm ESP32 detects TP14 low. |
| Wi-Fi control | Confirm ESP32 joins Wi-Fi and keeps audio path running if Wi-Fi drops. |
Open Bring-Up Risks
- Initial 18 V / 2 A adapter cannot sustain continuous 30 W + 30 W output.
- Final passive MPNs/packages must be selected before production assembly.
- TAS5825M PPC3/register configuration is required before meaningful audio validation.
Prerequisites
1. Visual Inspection
2. Power Rail Verification
3. Critical Signals
4. Connector Tests
5. Programming
6. Functional Validation
Open Bring-Up Risks
