Stereo DSP Amplifier
Worked for 13 mins 30 sec
I’m blocked because your account has no available ACUs, so AI execution tools are unavailable and I can’t continue routing or running final checks right now.
Accomplished so far:
- Applied the uploaded BOM MPNs/footprint fields to the project properties as provided.
- Changed the PCB from 200 × 200 mm to 100 × 100 mm, 4-layer stackup with Layer 2 as ground and Layer 3 as power.
- Re-placed all 141 components on the 100 × 100 mm board with functional separation: analog inputs left, ESP32 top edge, Class-D/output stage right, power/regulators bottom/right.
- Placement is mostly cleaned up, but 3 decoupling-loop warnings remained after the last placement pass: C14, C26, C33.
Open items:
- Route every net.
- Resolve remaining placement/DRC warnings.
- Run final ERC/DRC.
- Confirm whether the custom footprint names from the spreadsheet are accepted by manufacturing/export, since some were set exactly but reported as non-standard property values.
Suggested next steps once ACUs are available:
- Fix C14/C26/C33 placement warnings.
- Run pre-route board check.
- Auto-route the board.
- Run final ERC/DRC and clean remaining issues.
Fix capacitor placement
Check footprint exports
Manual capacitor help
Check board boundary
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Design Notes — Stereo DSP Amplifier
Schematic Status
- Complete schematic and BOM draft created for the requested signal chain.
- PCB placement and routing were intentionally not performed.
- Electrical ERC checks are clean as of 2026-07-25.
- Manufacturing/BOM checks still report missing manufacturer part numbers for generic passives, generic test points, generic inductors, and the 1x4 attenuation headers. These need final orderable MPN/package selections before manufacturing export.
Fixed Major Components
Table
| Ref | Function | MPN | Notes |
|---|---|---|---|
| U1 | Dual balanced line receiver | INA1650IPWR | Fixed by requirement, powered from +12V_A single supply for improved headroom. |
| U2 | Stereo ADC | PCM1863DBT | Fixed by requirement. TI DBT TSSOP-30 is 0.65 mm pitch; the library metadata should be re-verified at layout. |
| U3 | DSP/Wi-Fi MCU | ESP32-S3-WROOM-1-N16R8 | I2S master, Wi-Fi control, I2C configuration, FAULT monitoring. |
| U4 | Stereo Class-D amplifier | TAS5825MRHBR | 18V PVDD, 3.3V DVDD, BTL LC output filters. |
Power Architecture
Table
| Rail | Source | Loads | Design Notes |
|---|---|---|---|
| 18V_RAW | J3 DC barrel | F1 input fuse | PJ-102AH supports 5A; initial adapter may be 2A. |
| 18V_PROTECTED / PVDD_18V | F1 + Q1 reverse protection + D1 TVS | TAS5825M PVDD, U5 buck, U6 LDO | Net annotated for 5A future adapter path. |
| 3V3 | U5 TPS54302 buck | ESP32-S3, PCM1863 DVDD/IOVDD, TAS5825M DVDD, I2C pullups | 3A-capable regulator; budget target >=1A peak for ESP32 Wi-Fi bursts plus audio ICs. |
| ADC_AVDD_3V3 | 3V3 through FB1 ferrite bead | PCM1863 AVDD | Filtered analog branch to keep ESP32/buck noise away from ADC analog/reference. |
| 12V_A | U6 TPS7A4901 LDO | INA1650 VCC | Low-noise 12V rail selected instead of 5V to improve balanced-line input headroom. |
Preliminary Power Budget
Table
| Rail | Main Loads | Estimated Peak |
|---|---|---|
| 18V_PROTECTED | TAS5825M PVDD plus regulator input power | Up to 5A path design target; 2A adapter will not sustain 30W+30W. |
| 3V3 | ESP32-S3 Wi-Fi peaks, PCM1863 digital/I/O, TAS5825M DVDD, I2C | ~0.7–1.0A peak design target. |
| ADC_AVDD_3V3 | PCM1863 analog | <100mA target. |
| 12V_A | INA1650 quiescent/current headroom | <50mA target. |
Audio/Input Decisions
- TRS sleeve terminals are on CHASSIS_SHIELD with R40/C59 provisional RF/bleed connection to circuit GND.
- D2/D3 are PESD15VS2UT dual-line ESD protectors; VRWM is 15V and capacitance is about 32pF typical, acceptable for audio but not ultra-low compared with high-speed ESD arrays.
- Balanced input pad is jumper-selectable per leg using J7–J10. Pin 1 is common to the INA input; pins 2/3/4 select 0dB, -10dB, or -18dB paths respectively. Use one shunt position per leg and match L/R hot/cold settings.
- INA1650 REF/COM pins use the internal VMID(OUT) reference for single-supply operation.
- INA outputs are AC-coupled and RC-filtered into PCM1863 VINL1/VINR1 single-ended ADC inputs.
Digital Audio / Control Pin Map
Table
| Function | ESP32 GPIO | Net | Destination |
|---|---|---|---|
| I2S BCLK | IO4 | I2S_BCLK | U2 BCK, U4 SCLK via R12 source resistor |
| I2S LRCLK | IO5 | I2S_LRCLK | U2 LRCK, U4 LRCLK via R13 source resistor |
| ADC DOUT | IO6 | ADC_DOUT | U2 DOUT via R14 series resistor |
| Amp SDIN | IO7 | AMP_SDIN | U4 SDIN via R15 series resistor |
| I2C SDA | IO8 | I2C_SDA | U2 MD2/SDA, U4 SDA |
| I2C SCL | IO9 | I2C_SCL | U2 MD3/SCL, U4 SCL |
| Amp FAULT | IO10 | AMP_FAULT | U4 GPIO0 |
| Amp PDN | IO11 | AMP_PDN | U4 ~PDN, held low by R9 until firmware enables |
| Amp warn/mute GPIO | IO12 | AMP_WARN_OR_MUTE | U4 GPIO1 |
| ESP reset | EN | ESP_EN_RESET | SW1/J6/TP13 |
| ESP boot | IO0 | ESP_BOOT | SW2/J6 |
Layout Risks to Address Later
- Verify the PCM1863DBT land pattern against TI DBT 0.65 mm pitch before placement.
- Validate output inductor MPNs for saturation/current/thermal performance at 18V into 4Ω.
- Confirm final generic passive packages and MPNs before manufacturing export.
- Keep ESP32 antenna at the board edge with keepout on all copper layers.
- Keep analog input/ADC far from TAS output filters and switching regulator loops.
Schematic Status
Fixed Major Components
Power Architecture
Preliminary Power Budget
Audio/Input Decisions
Digital Audio / Control Pin Map
Layout Risks to Address Later
