• Product: SmarTemp+ standard
• Board: TCS-SC-Core-Baseboard-v1
• Status: REV-FINAL schematic capture; Netlist/PinMap + BOM PDFs are authoritative.
• Purpose: ESP32-S3 controller/baseboard for 4 thermocouple channels, external SSR control, CAN, wireless connectivity, 3.5 inch QSPI display mezzanine, and LiPo-backed 12V/USB-C power.

1. TCS-SC_Core_Netlist_PinMap.pdf — authoritative pin map, netlist, footprints, and design rules.
2. TCS-SC_Core_BOM.pdf — authoritative POP/DNP BOM.
3. TCS-SC_Core_FLUX_SUBMISSION.pdf — capture workflow and implementation notes.

• Prototype/production-intent SELV controller for SmarTemp+ standard.
• Mains switching is performed by external isolated SSR modules; mains is not routed on this baseboard.
• Prototype finish: ENIG. Volume finish target: immersion silver if assembly yield and storage requirements allow.

• Read 4 thermocouple channels through MAX31856 converters.
• Drive 8 SSR control positions through an I2C expander and 2N7002 low-side drivers; channels 1-2 populated for v1, 3-8 DNP.
• Communicate over ESP32-S3 WiFi/BLE, ESP32-C6 stock esp-hosted WiFi6/Thread/Matter over SPI, and CAN/TWAI.
• Host a 3.5 inch 320x480 Startek AXS15231 QSPI display on a 40-pin DF40 FRU mezzanine.
• Provide PWM piezo beeper alerts on GPIO16.
• Operate primarily from 12V, optionally USB-C, with LiPo backup through AXP2101 ORed into VSYS.

• Main MCU: ESP32-S3-WROOM-1-N16R8.
• Radio co-processor: ESP32-C6-MINI-1 over SPI esp-hosted.
• Thermocouples: 4x MAX31856MUD+ on shared HSPI/SPI3 with direct chip selects.
• Display: Startek KD035QVFID225-C086A / AXS15231, QSPI-strapped mezzanine.
• CAN: SN65HVD230, PESD1CAN TVS, common-mode choke, Phoenix terminal.
• I/O expanders: TCA9555 @0x21 for SSR/IO; TCA9554 @0x20 for peripheral IO; both polled.
• Peripherals: PCF85063A RTC @0x51 with CR1220; 24AA02 mezzanine ID EEPROM @0x50; Qwiic I2C; spare GPIO47/48 header.
• DNP insurance: MCP2518FD CAN-FD land, tire SELV loop front end, microSD, opto/isolator SSR options, alternate AFE lands.

Diagram

• ESP32-S3-WROOM-1-N16R8 is the main controller.
• USB-C D+/D- connect to GPIO20/GPIO19 through 22 ohm series resistors and ESD.
• CC pins require 5.1k pull-downs for sink behavior.
• BOOT on GPIO0 with 10k pull-up and button to GND.
• EN/reset with 10k pull-up, 1uF to GND, and reset button.

• +12V barrel input goes through reverse-polarity P-FET, SMBJ24A TVS, and polyfuse.
• LM66100 ideal-OR combines 12V-primary path and USB 5V path into VSYS; AXP2101 SYS also ORs battery backup into VSYS.
• MP2315 bucks VSYS to +5V.
• AP63203 bucks +5V to +3V3 and is the only +3V3 source.
• AXP2101 is PMU/charger/backup only; it is not the system 3.3V regulator.
• +3V3_A is derived through FB1 for the MAX31856 analog island.

• 4x MAX31856MUD+ powered from +3V3_A and GND_A.
• Shared TC_SCK GPIO17, TC_MOSI GPIO18, TC_MISO GPIO21.
• Direct CS: GPIO38/39/40/41.
• FAULT pins wire-OR to GPIO42 with 10k pull-up.
• Each input has RC C0G filtering and SM712-class TVS; keep analog island thermally and electrically quiet.
• GND_A star-ties to GND at the power-supply return, not under U1.

• ESP32-C6-MINI-1 stock esp-hosted slave firmware.
• SPI link: GPIO9 SCK, GPIO10 MOSI, GPIO11 MISO, GPIO13 CS, GPIO14 handshake, GPIO15 reset.
• Dual-band antenna provision DNP for future ESP32-C5/5GHz option.

• ESP32-S3 TWAI: GPIO43 TX, GPIO44 RX.
• SN65HVD230 transceiver with PESD1CAN TVS and CAN common-mode choke to J_CAN.
• MCP2518FD CAN-FD footprint is DNP for future demand.

• TCA9555 @0x21 drives 8 SSR low-side 2N7002 channels.
• J_SSR1-2 populated; J_SSR3-8 and related parts DNP for v1.
• Opto/digital-isolator lands DNP because external SSRs are self-isolated.
• Tire SELV loop front end is DNP insurance for v1: TPS2553, INA181, TLV7011, ADS1115 @0x48, sense resistors, and warmer loop connectors.

• 40-pin Hirose DF40C-40DS B2B mezzanine connector.
• QSPI display nets: IO0-3 GPIO1-4, SCLK GPIO5, LCD_CS GPIO12, BL_PWM GPIO6.
• I2C, touch INT/RST, power, mezz-ID EEPROM, and reserved lines route through the B2B.
• PCF85063A RTC @0x51 with 32.768kHz crystal and CR1220 backup.
• Qwiic connector on global I2C.
• GPIO47/48 to spare header. GPIO45/46 are strap/test-point only.

• USB-C: native USB programming/debug and USB 5V source.
• 12V barrel: primary SELV input.
• LiPo JST: backup battery with pack PCM, UN38.3/IEC62133 requirement.
• Thermocouple inputs: 4 channels via warmer cable terminals.
• SSR terminals: low-voltage control only, external isolated SSRs.
• CAN terminal: CANH/CANL with protection/filtering.
• Display mezzanine: DF40 40-pin FRU boundary.
• Qwiic: I2C expansion.
• Spare GPIO header: GPIO47/48.

• Primary operating source: 12V.
• USB-C supports programming and limited operation depending host current.
• LiPo provides backup through AXP2101 and VSYS ORing.
• Current budget must include two radios, display/backlight, MAX31856 island, expanders, CAN, and SSR controls before final fuse/inductor/regulator validation.

• +12V: barrel input, reverse/FET/TVS/fuse path.
• VSYS: ORed source node feeding MP2315.
• +5V: MP2315 output; powers AP63203 input, mezzanine backlight boost, and optional tire SELV.
• +3V3: AP63203 output only; powers MCU, C6, CAN logic, I2C peripherals, expanders, RTC, EEPROM, and Qwiic.
• +3V3_A: ferrite-filtered thermocouple analog rail.
• VBAT: LiPo into AXP2101.

• 4-layer PCB: L1 signal / L2 GND / L3 PWR / L4 signal.
• Board size: 130 x 90 mm.
• Include 4x M3 plus 2 midpoint mounting points.
• Prefer MLCC 105C with 2x capacitance derating; C0G for thermocouple analog filters; no electrolytics.
• Selective conformal coat over thermocouple island.

• ESP-IDF/ESP32-S3 native USB-CDC programming.
• SecureBootV2, flash encryption, signed OTA, encrypted NVS planned for production.
• Pin map is locked: 29/31 usable GPIO, GPIO47/48 spare.
• I2C devices: TCA9554 0x20, TCA9555 0x21, AXP2101 0x34, ADS1115 0x48 DNP, 24AA02 0x50, PCF85063A 0x51, touch via B2B, Qwiic.
• C6 remains stock esp-hosted, no custom firmware fork.

• ESP32-S3 and ESP32-C6 antennas at opposite corners with copper keepouts.
• Thermocouple analog island away from buck inductor, QSPI, SSR FETs, and radio sections.
• QSPI through B2B needs ground guards, source series-term footprints, and length awareness; 32MHz fallback accepted.
• CAN port requires TVS and common-mode choke near connector.
• Buck loop areas must be minimized.

• Use ESP32 module-down approach for RF risk reduction.
• Use direct MAX31856 CS lines; no decoder.
• Use simple PWM piezo instead of ES8311 audio codec.
• Use AP63203 as the sole 3.3V source; AXP2101 is not a 3.3V source.
• Use SN65HVD230 as customer-demanded CAN transceiver.
• Keep tire SELV and CAN-FD hooks as DNP insurance.

• Per-rail current budget is still to be finalized with datasheet worst-case currents.
• Startek AXS15231 QSPI strap/order option must be confirmed with supplier.
• Display mezzanine touch INT/RST exact pins must be finalized from mezzanine connector pinout.
• EE review is required for TC island, QSPI B2B routing, antenna coexistence, power tree, and CAN protection before Gerbers.

• 2026-05-29: Initial requirements imported from user table.
• 2026-05-29: REV-FINAL PDFs imported. Specification now supersedes earlier assumptions: C6-MINI-1, SN65HVD230, TCA9555/TCA9554, PCF85063A, MP2315/AP63203/LM66100 power tree, 8 SSR positions with v1 POP/DNP split, DF40 40-pin display mezzanine, and DNP tire/CAN-FD insurance blocks.