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External host/controller
   | 5V_IN, SPI, HC595 control, reset/status
   v
J9/J10 interface headers
   |----------------------------------------------------|
   |                                                    |
   v                                                    v
U10 3V3 regulator                              U4 74HC595 control expander
   | 3V3                                            | QA..QD mode controls
   |                                                v
   |                                         U6 CD4066 analog switch matrix
   |                                                |
Field input J1 -> D1 TVS -> R1 series -> UI1_PROT ----+---- 0-10V divider R2/R3 -> ADC path
                                                       +---- 0-20mA shunt R4 -> ADC path
                                                       +---- sensor excitation R5 -> ADC path
                                                       +---- digital sense -> LM2903 comparator

ADC path: U6 selected node -> UI1_ADC -> C10 filter -> U2 AD7708 AIN1
Reference/clock: IC1 LM4040 2.5V -> U2 REFIN1(+), Y1/C23/C24 -> U2 XTAL1/XTAL2
Digital path: UI1_DIG_SENSE -> U3A comparator -> UI1_DIG_OUT
Field power protection: FIELD_24V_IN -> U1 LM76202 -> FIELD_24V_PROT, FIELD_FLT_N status

• J1 pin 1 is UI1_FIELD, the field signal input.
• J1 pin 2 is GND/return.

• SPI_SCLK goes to AD7708 SCLK and HC595 SRCLK.
• SPI_MOSI goes to AD7708 DIN and HC595 SER.
• SPI_MISO comes from AD7708 DOUT.
• ADC_CS_N selects the AD7708.
• ADC_RDY_N reports when the AD7708 conversion data is ready.
• ADC_RESET_N resets the AD7708.
• HC595_LATCH, HC595_SRCLR_N, and HC595_OE_N control the shift register output latch, clear, and output-enable states.
• UI1_DIG_OUT reports the comparator-backed digital input result.
• FIELD_FLT_N reports LM76202 field-power fault status.

• U10: 3.3 V regulator.
• C19 = 10 µF: bulk/input capacitor on 5V_IN near U10.
• C20 = 10 µF: regulator output capacitor on 3V3.
• C18 = 100 nF: additional local decoupling/filtering on 5V_IN.

• FIELD_24V_IN feeds U1 IN.
• U1 OUT creates FIELD_24V_PROT.
• FIELD_FLT_N is the active-low fault/status output.

1. J1 pin 1 is UI1_FIELD.
2. D1 SM6T18A TVS clamps UI1_FIELD to GND for surge/transient protection.
3. R1 = 1 kΩ connects UI1_FIELD to UI1_PROT, limiting current into the measurement network.
4. UI1_PROT feeds the selectable measurement paths.

• R2 = 30 kΩ from UI1_PROT to UI1_0_10V_DIV.
• R3 = 10 kΩ from UI1_0_10V_DIV to GND.

• R4 = 165 Ω from UI1_PROT to GND.

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V = I × R = 0.020 A × 165 Ω = 3.3 V

• R5 = 10 kΩ is the sensor excitation resistor.
• U6 connects 3.3 V to UI1_EXCITE_SRC under CTRL_RESISTANCE_MODE.
• R5 then pulls/excites UI1_PROT.
• The resulting divider voltage is measured by the AD7708 at UI1_ADC.

• U6 connects UI1_PROT to UI1_DIG_SENSE under CTRL_DIGITAL_MODE.
• UI1_DIG_SENSE goes to U3A, the first comparator inside the LM2903.
• U3A compares the input against DIG_THRESHOLD.
• UI1_DIG_OUT is the logic-level digital status output.

• R29 = 100 kΩ from 3.3 V to DIG_THRESHOLD.
• R30 = 100 kΩ from DIG_THRESHOLD to GND.

• R25 = 10 kΩ pull-up to 3.3 V.
• UI1_DIG_OUT to the host/control header.

• AIN1 is connected to the selected universal-input analog node UI1_ADC.
• AIN2 through other unused analog inputs are tied to GND for a defined state.
• REFIN1(+) is connected to the 2.5 V reference.
• REFIN1(-) is connected to GND.
• AVDD and DVDD are connected to 3.3 V.
• AGND, DGND, and AINCOM are connected to GND.
• SPI/control pins connect to the host headers.

• R21 = 2.2 kΩ biases the shunt reference from 3.3 V.
• IC1 cathode creates 2V5_REF.
• IC1 anode is tied to GND.
• C21 = 100 nF filters the reference.
• 2V5_REF goes to AD7708 REFIN1(+).

• C23 = 12 pF from ADC_XTAL1 to GND.
• C24 = 12 pF from ADC_XTAL2 to GND.

• C1/C2: AD7708 AVDD/DVDD decoupling.
• C3: LM2903 comparator supply decoupling.
• C4: HC595 decoupling.
• C6: CD4066 decoupling.
• C7/C8/C9/C18: additional local decoupling/filter capacitors from the earlier architecture.
• C10 = 100 nF: ADC input filter / charge bucket from UI1_ADC to GND.
• C21 = 100 nF: ADC reference filtering.
• C23/C24 = 12 pF: crystal load capacitors.
• C26 = 12 nF: LM76202 dVdT setting.
• C27 = 1 µF and C22 = 47 µF: LM76202 input/output bulk support.

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J1 pin 1 -> D1/R1 protection -> UI1_PROT -> R2/R3 divider -> UI1_0_10V_DIV -> U6A -> UI1_ADC -> U2 AIN1 -> SPI data to host

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J1 pin 1 -> D1/R1 protection -> UI1_PROT -> R4 shunt to GND -> U6B -> UI1_ADC -> U2 AIN1 -> SPI data to host

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3V3 -> U6C -> UI1_EXCITE_SRC -> R5 10k -> UI1_PROT -> sensor to GND/return through J1 -> U6/ADC path -> U2 AIN1 -> SPI data to host

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J1 pin 1 -> D1/R1 protection -> UI1_PROT -> U6D -> UI1_DIG_SENSE -> U3A comparator -> UI1_DIG_OUT -> host input

1. Drive the HC595 mode bits.
2. Ensure only one measurement mode is active at a time.
3. Configure the AD7708 for the expected input range and conversion mode.
4. Read ADC_RDY_N, then read ADC data over SPI.
5. Convert raw ADC codes into engineering units using the active mode:
   • 0–10 V: multiply ADC-measured divider voltage by 4.
   • 0–20 mA: compute current from shunt voltage / 165 Ω.
   • Resistance/RTD/thermistor: compute resistance from the divider equation, then apply RTD or thermistor calibration tables.
   • Digital input: read UI1_DIG_OUT, or optionally cross-check with ADC voltage.
6. Monitor FIELD_FLT_N if field-power protection status is relevant.

• Schematic/ERC categories checked so far are generally clean for the single-channel schematic.
• Current DRC still reports 2 airwire errors.
• Manufacturing review reports J9 missing manufacturer part number.

1. 0–20 mA full-scale voltage is about 3.3 V. With a 2.5 V reference, this needs ADC range confirmation or a lower shunt value if the AD7708 configuration cannot accept that input span.
2. PT1000/NI1000 sensitivity may be modest with a 10 kΩ excitation resistor. This is usable as an architecture, but final accuracy depends on ADC noise, excitation tolerance, and calibration.
3. Digital threshold is fixed around 1.65 V. If the intended digital input standard is 24 V industrial DI, the threshold/hysteresis/protection strategy should be reviewed.
4. CD4066 switch on-resistance and leakage affect precision. For higher-accuracy RTD/resistance measurements, switch resistance and leakage should be included in calibration/error budget.
5. The current design is non-isolated. Field input return shares board GND.
6. Routing is not fully complete yet. Latest review shows remaining airwire errors.
7. J9 metadata needs completion if manufacturing/BOM checks must pass cleanly.