Project Startup

flux

The architecture and power envelope are set. The schematic build is still in progress across the power, ESP32, radio, storage, IR, and protected debug blocks.
Thought for 11 mins 7 sec
Thought for 7 sec
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Received notification from "ESP32-S3 Toolkit Schematic" that it finished — picking the work back up.

flux

Built the Phase 1 modular proof-of-concept schematic with 156 components and 114 nets, covering ESP32-S3 compute, battery/USB-C power, NFC, sub-GHz, IR, microSD, UI, expansion, and protected debug interfaces. The project was renamed and a Phase 1 Power Budget was created.
Open items
  • Independent ERC/connectivity verification was not completed.
  • Any schematic errors found during review still need remediation.
  • Firmware pin mapping and starter code remain to be generated.
  • PCB layout has not started.
  • Work is paused because no ACUs are currently available.
Suggested next steps
  1. Replenish ACUs and run a full schematic/ERC review.
  2. Resolve any power, GPIO, or interface warnings.
  3. Generate firmware documentation from the finalized pin map.
  4. Review the schematic before proceeding to PCB layout.
Review and fix ERC
Check power budget
Create pin-map documentation
Prepare PCB layout
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Files

Schematic

Layout

Preview

U12
U6
U10
J3
J6
U11
U1
Manufacturer Part Number
ESP32-S3-WROOM-1-N16R8
U8
U7
U9
D1
U13
J1
U2
Phase 1 Power Budget
Design Envelope
The proof-of-concept uses a single-cell Li-ion/LiPo source, USB-C charging with power-path management, an always-available 3.3 V system rail, and a separately switched 5 V expansion/target rail. Exact figures must be replaced by measured prototype values before Phase 2.

Table

LoadRailSleep/OffTypical ActivePeak Design Allowance
ESP32-S3 module3.3 V20 µA180 mA500 mA
Outdoor color display + backlight3.3 V0100 mA180 mA
microSD3.3 V050 mA200 mA
NFC reader/writer module3.3 V080 mA150 mA
Sub-GHz transceiver module3.3 V035 mA150 mA
IR transmitter/receiver3.3 V030 mA200 mA pulsed
UI, haptic, buzzer, level shifting, indicators3.3 V5 µA80 mA200 mA
External target/USB-host allowance5 V switched0250 mA500 mA
Rail Totals
  • 3.3 V simultaneous design peak: 1.58 A. Size the regulator for at least 2 A continuous capability with transient margin.
  • 3.3 V representative mixed active load: approximately 555 mA before optional expansion loads.
  • Switched 5 V rail: 500 mA peak.
Battery-Side Worst Case
At a depleted-cell design voltage of 3.0 V:
  • 3.3 V rail peak through an assumed 90% efficient buck-boost: (3.3 V × 1.58 A) / (3.0 V × 0.90) ≈ 1.93 A.
  • 5 V rail peak through an assumed 85% efficient boost: (5 V × 0.50 A) / (3.0 V × 0.85) ≈ 0.98 A.
  • Combined theoretical simultaneous input peak: approximately 2.9 A, excluding converter transient and quiescent current.
The battery, protection circuit, power-path devices, connectors, and PCB copper should therefore tolerate at least 3 A, preferably 4 A, even though firmware should prevent unnecessary simultaneous activation of all high-current functions.
Energy Estimate
Using a 5000 mAh, 3.7 V battery (18.5 Wh nominal):
  • At a representative 2.5 W mixed-use load, ideal runtime is 7.4 h; allowing conversion losses and reserve gives roughly 5.5–6.5 h.
  • A full working day requires aggressive duty cycling, a larger battery, or reduced display/radio usage.
  • Multi-week standby requires every optional load to be power-gated and total battery-side sleep current to remain well below 100 µA.
Power Architecture Requirements
  1. USB-C sink input with independent CC resistors or a Type-C/PD controller and advertised-current detection.
  2. Charger with power-path/load-sharing, battery temperature input, and at least 2 A system capability.
  3. Battery protection and fuel gauge.
  4. 3.3 V buck-boost regulator rated at least 2 A.
  5. Separately enabled 5 V boost rated at least 500 mA output at minimum battery voltage.
  6. Load switches for display, SD, NFC, sub-GHz, IR, and external target power.
  7. Target power defaults off and includes current limiting.
  8. Firmware interlocks should prevent worst-case simultaneous loads unless USB input and thermal conditions permit it.
Validation
Measure each block in off, idle, receive, and transmit states. Recalculate regulator thermals, battery runtime, and enclosure temperature using measured data before miniaturizing the design.

  • Design Envelope

  • Rail Totals

  • Battery-Side Worst Case

  • Energy Estimate

  • Power Architecture Requirements

  • Validation