Project Startup

Thought

The architecture and power envelope are set. The schematic build is still in progress across the power, ESP32, radio, storage, IR, and protected debug blocks.

Thought for 11 mins 7 sec

Thought for 7 sec

Awaiting 1 background task

Received notification from "ESP32-S3 Toolkit Schematic" that it finished — picking the work back up.

Thought

flux

Built the Phase 1 modular proof-of-concept schematic with 156 components and 114 nets, covering ESP32-S3 compute, battery/USB-C power, NFC, sub-GHz, IR, microSD, UI, expansion, and protected debug interfaces. The project was renamed and a Phase 1 Power Budget was created.

Open items

Independent ERC/connectivity verification was not completed.
Any schematic errors found during review still need remediation.
Firmware pin mapping and starter code remain to be generated.
PCB layout has not started.
Work is paused because no ACUs are currently available.

Suggested next steps

Replenish ACUs and run a full schematic/ERC review.
Resolve any power, GPIO, or interface warnings.
Generate firmware documentation from the finalized pin map.
Review the schematic before proceeding to PCB layout.

Review and fix ERC

Check power budget

Create pin-map documentation

Prepare PCB layout

Files

Schematic

Layout

Preview

U12

U10

U11

Manufacturer Part Number

ESP32-S3-WROOM-1-N16R8

U13

Resistance

10kΩ

R55

Resistance

732kΩ

Resistance

10kΩ

R26

Resistance

1kΩ

R29

Resistance

1kΩ

R49

Resistance

59kΩ

R10

Resistance

10kΩ

R43

Resistance

33Ω

R18

Resistance

10kΩ

R17

Resistance

10kΩ

Resistance

10kΩ

Resistance

10kΩ

R48

Resistance

130Ω

R11

Resistance

10kΩ

R12

Resistance

10kΩ

R44

Resistance

33Ω

Resistance

10kΩ

R34

Resistance

1kΩ

R46

Resistance

33Ω

R24

Resistance

1kΩ

R20

Resistance

4.7kΩ

R58

Resistance

100kΩ

R15

Resistance

10kΩ

R36

Resistance

1kΩ

R56

Resistance

22Ω

Resistance

10kΩ

R13

Resistance

10kΩ

R45

Resistance

33Ω

R27

Resistance

1kΩ

R57

Resistance

100Ω

Resistance

10kΩ

R22

Resistance

1kΩ

R14

Resistance

10kΩ

Resistance

10kΩ

R47

Resistance

20mΩ

R32

Resistance

1kΩ

Resistance

10kΩ

R41

Resistance

33Ω

R53

Resistance

100kΩ

R30

Resistance

1kΩ

R21

Resistance

1kΩ

R42

Resistance

33Ω

R37

Resistance

33Ω

R38

Resistance

33Ω

R31

Resistance

1kΩ

R51

Resistance

100kΩ

R50

Resistance

100kΩ

R25

Resistance

1kΩ

R33

Resistance

1kΩ

R19

Resistance

4.7kΩ

R23

Resistance

1kΩ

R52

Resistance

100kΩ

R16

Resistance

10kΩ

R35

Resistance

1kΩ

R60

Resistance

100kΩ

R40

Resistance

33Ω

R28

Resistance

1kΩ

R39

Resistance

33Ω

R59

Resistance

200kΩ

R54

Resistance

312kΩ

C13

Capacitance

10uF

C20

Capacitance

10uF

C28

Capacitance

100nF

Capacitance

10uF

C17

Capacitance

10uF

Capacitance

10uF

C18

Capacitance

10uF

C40

Capacitance

100pF

C33

Capacitance

47nF

C11

Capacitance

10uF

C10

Capacitance

10uF

Capacitance

10uF

C26

Capacitance

100nF

C23

Capacitance

100nF

C36

Capacitance

1nF

C29

Capacitance

100nF

C38

Capacitance

1nF

C15

Capacitance

10uF

C24

Capacitance

100nF

Capacitance

10uF

C21

Capacitance

100nF

Capacitance

10uF

C34

Capacitance

1uF

C22

Capacitance

100nF

C32

Capacitance

100nF

C19

Capacitance

10uF

C35

Capacitance

1nF

Capacitance

10uF

C37

Capacitance

1nF

Capacitance

10uF

C12

Capacitance

10uF

Capacitance

10uF

C30

Capacitance

100nF

C25

Capacitance

100nF

C27

Capacitance

100nF

C31

Capacitance

100nF

Capacitance

10uF

C14

Capacitance

10uF

C16

Capacitance

10uF

C39

Capacitance

1nF

TP9

TP6

TP11

TP5

TP8

TP2

TP1

TP10

TP7

TP3

TP4

TP12

J11

U22

U18

U16

U15

U17

U19

U20

J10

SW2

Inductance

1.5uH

U21

Inductance

1uH

Inductance

2.2uH

SW1

U14

Phase 1 Power Budget

Design Envelope

The proof-of-concept uses a single-cell Li-ion/LiPo source, USB-C charging with power-path management, an always-available 3.3 V system rail, and a separately switched 5 V expansion/target rail. Exact figures must be replaced by measured prototype values before Phase 2.

Table

Load	Rail	Sleep/Off	Typical Active	Peak Design Allowance
ESP32-S3 module	3.3 V	20 µA	180 mA	500 mA
Outdoor color display + backlight	3.3 V	0	100 mA	180 mA
microSD	3.3 V	0	50 mA	200 mA
NFC reader/writer module	3.3 V	0	80 mA	150 mA
Sub-GHz transceiver module	3.3 V	0	35 mA	150 mA
IR transmitter/receiver	3.3 V	0	30 mA	200 mA pulsed
UI, haptic, buzzer, level shifting, indicators	3.3 V	5 µA	80 mA	200 mA
External target/USB-host allowance	5 V switched	0	250 mA	500 mA

Rail Totals

3.3 V simultaneous design peak: 1.58 A. Size the regulator for at least 2 A continuous capability with transient margin.
3.3 V representative mixed active load: approximately 555 mA before optional expansion loads.
Switched 5 V rail: 500 mA peak.

Battery-Side Worst Case

At a depleted-cell design voltage of 3.0 V:

3.3 V rail peak through an assumed 90% efficient buck-boost: (3.3 V × 1.58 A) / (3.0 V × 0.90) ≈ 1.93 A.
5 V rail peak through an assumed 85% efficient boost: (5 V × 0.50 A) / (3.0 V × 0.85) ≈ 0.98 A.
Combined theoretical simultaneous input peak: approximately 2.9 A, excluding converter transient and quiescent current.

The battery, protection circuit, power-path devices, connectors, and PCB copper should therefore tolerate at least 3 A, preferably 4 A, even though firmware should prevent unnecessary simultaneous activation of all high-current functions.

Energy Estimate

Using a 5000 mAh, 3.7 V battery (18.5 Wh nominal):

At a representative 2.5 W mixed-use load, ideal runtime is 7.4 h; allowing conversion losses and reserve gives roughly 5.5–6.5 h.
A full working day requires aggressive duty cycling, a larger battery, or reduced display/radio usage.
Multi-week standby requires every optional load to be power-gated and total battery-side sleep current to remain well below 100 µA.

Power Architecture Requirements

USB-C sink input with independent CC resistors or a Type-C/PD controller and advertised-current detection.
Charger with power-path/load-sharing, battery temperature input, and at least 2 A system capability.
Battery protection and fuel gauge.
3.3 V buck-boost regulator rated at least 2 A.
Separately enabled 5 V boost rated at least 500 mA output at minimum battery voltage.
Load switches for display, SD, NFC, sub-GHz, IR, and external target power.
Target power defaults off and includes current limiting.
Firmware interlocks should prevent worst-case simultaneous loads unless USB input and thermal conditions permit it.

Validation

Measure each block in off, idle, receive, and transmit states. Recalculate regulator thermals, battery runtime, and enclosure temperature using measured data before miniaturizing the design.

Design Envelope
Rail Totals
Battery-Side Worst Case
Energy Estimate
Power Architecture Requirements
Validation