Project Startup

Worked for 3 mins
Thought for 16 sec
Managing assets.
Thought for 17 sec — Gathering documentation and schematics
Reading project docs.
Thought for 13 sec
Getting a schematic overview for ESP32.
Thought for 12 sec
Reading schematic details while tracing connections from U1.
Thought for 16 sec — Considering pin mappings
Reading schematic details for U1.
Thought for 47 sec — Creating project documentation
Updating 2 project docs.
Created 2 project docs

Firmware Starter — ESP32-S3-WROOM-1-N16R8

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Firmware Starter — ESP32-S3-WROOM-1-N16R8 Platform & Toolchain
  • MCU: U1, ESP32-S3-WROOM-1-N16R8
  • Framework: Arduino-ESP32 through PlatformIO
  • Purpose: Safe board bring-up firmware. Peripheral rails default off; transmit-capable modules require explicit user action.
Pin Mapping
Low-speed power enables, isolation controls, buttons, presence inputs, and night-mode control are provided through TCA9535 expanders U23 and U32 on the system I2C bus. Their exact port roles are defined by the net names in the schematic and must remain default-off until configured.
platformio.ini Complete Starter Source — src/main.cpp Build & Flash
Set SW3 to DOWNLOAD or hold BOOT (SW2) while resetting (SW1) to enter the ROM bootloader. Return SW3 to NORMAL after ...

Board Bring-Up Plan

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Board Bring-Up Plan Prerequisites
  • Bench supply with current limit, DMM, oscilloscope, USB current meter, thermal camera, USB data isolator, logic analyzer, known-good 1S protected packs, and ESD-safe workstation.
  • Use the Firmware Starter safe bring-up image.
  • Start without NFC, sub-GHz, display, removable storage, debug target, microphone, speaker, or expansion modules attached.
1. Visual and Unpowered Inspection
  • Verify orientation and soldering of U1–U38, D1–D5, Q1, F2/F3, polarized battery connectors, USB-C J1, microSD J3, and switches SW1–SW3.
  • Confirm no conductive debris beneath shielded modules or connectors.
  • Measure resistance from USB_VBUS, PACK_A_FUSED, PACK_B_FUSED, VBAT, VSYS, 3V3, 5V_BOOST, and 5V_TARGET to GND. Investigate readings below 10 ohms befo...
M

macswim

Can it have a keyboard

flux

Yes. I’ll include a compact, glove-tolerant thumb QWERTY keyboard in the handheld concept, plus the existing directional controls and dedicated power/back keys. It will connect through the I/O expander as a scanned key matrix so it uses few ESP32 pins and can wake the device from sleep.

flux

The concept image is saved, and I created the Firmware Starter and Board Bring-Up Plan.
Before placement, confirm this layout plan:
  • Main PCB: retain 160 × 100 mm, four layers, standard through-vias.
  • Keyboard: separate front-panel thumb-QWERTY matrix PCB connected through the I/O expander; directional, power, and back controls remain dedicated.
  • Top side: MCU, power stages, radios/modules, SD, connectors, switches, and tall components.
  • Bottom side: small passives only.
  • Edges: USB-C and SD accessible at the front; debug/expansion ports along one side; batteries and emergency-isolation interfaces opposite; antennas separated along the rear edge.
  • RF: dedicated NFC, sub-GHz, and ESP32 antenna keepouts.
  • Manufacturing: standard 1 oz copper, no HDI or microvias; compatible with mainstream prototype fabs.
Reply confirmed to start placement and routing, or specify a different board size or keyboard arrangement.
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Files

Schematic

Layout

3D View

Board Bring-Up Plan
Prerequisites
  • Bench supply with current limit, DMM, oscilloscope, USB current meter, thermal camera, USB data isolator, logic analyzer, known-good 1S protected packs, and ESD-safe workstation.
  • Use the Firmware Starter safe bring-up image.
  • Start without NFC, sub-GHz, display, removable storage, debug target, microphone, speaker, or expansion modules attached.
1. Visual and Unpowered Inspection
  • Verify orientation and soldering of U1–U38, D1–D5, Q1, F2/F3, polarized battery connectors, USB-C J1, microSD J3, and switches SW1–SW3.
  • Confirm no conductive debris beneath shielded modules or connectors.
  • Measure resistance from USB_VBUS, PACK_A_FUSED, PACK_B_FUSED, VBAT, VSYS, 3V3, 5V_BOOST, and 5V_TARGET to GND. Investigate readings below 10 ohms before power.
  • Verify emergency isolation switches are in NORMAL and SW3 is in NORMAL.
2. Power Rail Verification

Table

RailSourceExpectedInitial limitProbe
USB_VBUSJ15.0 V ±5%100 mATP1
PACK_A_FUSEDPack A/F23.0–4.2 V100 mAJ14 pin 1
PACK_B_FUSEDPack B/F33.0–4.2 V100 mAJ13 pin 1
VBATU28 dual-battery muxSelected pack voltage150 mATP3
VSYSU2 charger/power pathabout 3.5–4.4 V200 mATP2
3V3_PRE_SHUNTU33.3 V ±3%250 mATP4
3V3current-sense output3.3 V ±3%250 mATP5
5V_BOOSTU4, disabled by default5.0 V ±5%150 mATP6
5V_TARGETU5, disabled by default5.0 V ±5%100 mATP7
Sequence
  1. Power J1 from a current-limited 5 V source at 100 mA with no battery. Stop on current limit, smoke, odor, or >60 °C hotspot.
  2. Confirm USB_VBUS, VSYS, 3V3_PRE_SHUNT, and 3V3 in that order. Ripple target: <100 mVpp on 3V3 during boot.
  3. Confirm 5V_BOOST, 5V_TARGET, and all switched 3.3 V rails remain off.
  4. Raise the USB limit gradually to 500 mA only after stable rails are confirmed.
  5. Repeat from Pack A only, Pack B only, then both packs. Remove one pack while operating and verify VBAT/VSYS do not reset or overshoot.
  6. Operate each guarded isolation switch independently and verify only the selected pack is disconnected.
  7. Attach the external 10 kΩ NTC to J11 before charge-current testing. Verify charger thermal regulation and charge status.
3. Boot, Reset, and Programming
  • SW3 NORMAL: reset with SW1 and confirm normal boot.
  • SW3 DOWNLOAD or SW2 held during SW1 reset: confirm esptool.py chip_id detects ESP32-S3.
  • Flash with pio run -t upload; verify 115200-baud diagnostics over native USB.
  • Confirm MCU_EN idles high and MCU_BOOT idles high in NORMAL mode.
4. Critical Interfaces

Table

InterfaceNetsTest
Native USBUSB_D_P, USB_D_NEnumerate CDC, repeated connect/disconnect, check ESD array heating
I2CI2C_SDA/IO8, I2C_SCL/IO9Scan bus; confirm charger, gauge, monitors, TUSB320, U23 and U32
SPI backboneSPI_CLK/IO12, SPI_MISO/IO13, SPI_MOSI/IO111 MHz logic-analyzer check before raising clock
UART0UART_TX, UART_RX115200 8N1 loopback at J8
microSDJ3, 3V3_SD_SWEnable rail, verify card detect, initialize at low speed, read/write/verify 1 MB
DisplayJ6, 3V3_DISPLAY_SWEnable rail and isolator, display color bars, test night mode and controls
NFCJ4, 3V3_NFC_SWEnable only with module attached; read authorized test tag
Sub-GHzJ5, 3V3_SUBGHZ_SWReceive test first; transmit only into legal test setup or shielded load
Protected target portJ7, VTGTVerify no target power by default; test 1.8/3.3/5 V translation with current-limited fixture
ExpansionJ8Continuity, rail gating, bus loopback
Storage bayJ16, 3V3_STORAGE_SWPresence detect, SPI loopback/read test, hot insertion only when firmware permits
5. Functional Blocks
  • Verify MAX17048 voltage and state-of-charge response.
  • Verify dual-pack voltage monitors, presence inputs, charger status inputs, and mux status through U31/U32.
  • Confirm every TPS22918 switched rail powers up and discharges down independently.
  • Check IR receive, then transmit into a nearby detector; limit LED duty cycle.
  • Verify microphone I2S capture and speaker amplifier at minimum volume before acoustic coupler testing.
  • Verify red-light/night mode does not unintentionally enable the main backlight.
  • Test buttons, boot selector, card detect, emergency isolation switches, and target-power fault reporting.
  • Confirm Wi-Fi scan and BLE advertising separately; keep NFC and sub-GHz disabled during baseline RF tests.
6. Thermal, Power, and Environmental Screening
  • Log USB-only, single-pack, and dual-pack current in idle, active UI, SD write, NFC, sub-GHz receive, and each controlled transmit state.
  • Run 30 minutes at worst-case intended load; no IC or connector should exceed its rated temperature and enclosure-touch surfaces should remain below 55 °C.
  • Verify deep sleep with all switched rails off and compare to the Phase 1 power budget.
  • After electrical pass, perform condensation-free cold/heat functional checks from -10 °C to +50 °C with battery operation restricted to the cell manufacturer's limits.
  • Splash testing is enclosure-level and must not be performed on an unsealed, energized PCB.
7. Pass/Fail Summary

Table

SectionPassNotes
Visual/unpowered[ ]
USB and battery power[ ]
Dual-pack hot swap/isolation[ ]
3.3 V and switched rails[ ]
Programming/boot controls[ ]
USB/I2C/SPI/UART[ ]
SD/display/UI[ ]
NFC/sub-GHz/IR[ ]
Protected target interface[ ]
Audio/acoustic link[ ]
Thermal and sleep power[ ]
Board status: [ ] ready for controlled field prototype use [ ] requires rework

  • Prerequisites

  • 1. Visual and Unpowered Inspection

  • 2. Power Rail Verification

  • Sequence

  • 3. Boot, Reset, and Programming

  • 4. Critical Interfaces

  • 5. Functional Blocks

  • 6. Thermal, Power, and Environmental Screening

  • 7. Pass/Fail Summary