Healer+ Security toolkit -cyber-deck

Worked for 1 min 44 sec

For 5 assembled prototype PCBs with ENIG finish and through-hole assembly:

Table

Builder	PCB + assembly	Shipping	Delivered total	Per PCB
JLCPCB	$72.50	$10.41 standard / $27.06 UPS	$82.91–$99.56	$16.58–$19.91
PCBWay	$261.18	$5–$20	$266.18–$281.18	$53.24–$56.24

Estimated complete prototype cost

Allow approximately $150–$300 per finished handheld, once you include:

Display, batteries, keyboard and antenna hardware
Enclosure, captive fasteners and internal storage
Unavailable/substituted BOM parts
Wiring, final mechanical assembly and testing

This excludes engineering time, certification and production tooling.

Recommended build route

JLCPCB — PCB fabrication and assembly; currently the best-value option.
JLC3DP or PCBWay 3D — rugged prototype enclosure.
Local/manual integration — batteries, antennas, display, keyboard, switches and enclosure assembly.

The current PCB layout is not yet manufacturing-ready, so these are budgeting quotes—not an order recommendation yet. Placement, routing, DRC, BOM availability and mechanical fit must be completed before purchasing.

macswim

okay continue with the wrap up

Thought for 38 sec

flux

I’m closing the remaining manufacturing gates now: live layout audit, placement, routing, final DRC/ERC, and fabrication package if the board reaches a clean state.

Worked for 13 mins 26 sec

Thought for 12 sec

Getting a layout overview.

Thought for 11 sec

Completed design checks — found 976 issues.

Thought for 18 sec — Figuring out placement details

Awaiting 1 task

"PCB Placement Done" completed.

Thought for 4 sec

flux

Placement advanced substantially: all 245 components are now inside the 160 × 100 mm board, 37 overlaps were cleared, and all three switching-regulator stages pass their required placement checks.

Remaining work

Resolve 3 component overlaps.
Repair U1’s self-intersecting antenna keepout.
Review the microSD edge-offset warning and three L4 pad-access advisories.
Generate neckdowns and protected USB-C breakout.
Route the PCB and run final DRC/ERC.
Export Gerbers, BOM, and pick-and-place files only after DRC is clean.

Execution stopped because your ACUs ran out.

Files

Schematic

Layout

3D View

Board Bring-Up Plan

Prerequisites

Bench supply with current limit, DMM, oscilloscope, USB current meter, thermal camera, USB data isolator, logic analyzer, known-good 1S protected packs, and ESD-safe workstation.
Use the Firmware Starter safe bring-up image.
Start without NFC, sub-GHz, display, removable storage, debug target, microphone, speaker, or expansion modules attached.

1. Visual and Unpowered Inspection

Verify orientation and soldering of U1–U38, D1–D5, Q1, F2/F3, polarized battery connectors, USB-C J1, microSD J3, and switches SW1–SW3.
Confirm no conductive debris beneath shielded modules or connectors.
Measure resistance from USB_VBUS, PACK_A_FUSED, PACK_B_FUSED, VBAT, VSYS, 3V3, 5V_BOOST, and 5V_TARGET to GND. Investigate readings below 10 ohms before power.
Verify emergency isolation switches are in NORMAL and SW3 is in NORMAL.

2. Power Rail Verification

Table

Rail	Source	Expected	Initial limit	Probe
USB_VBUS	J1	5.0 V ±5%	100 mA	TP1
PACK_A_FUSED	Pack A/F2	3.0–4.2 V	100 mA	J14 pin 1
PACK_B_FUSED	Pack B/F3	3.0–4.2 V	100 mA	J13 pin 1
VBAT	U28 dual-battery mux	Selected pack voltage	150 mA	TP3
VSYS	U2 charger/power path	about 3.5–4.4 V	200 mA	TP2
3V3_PRE_SHUNT	U3	3.3 V ±3%	250 mA	TP4
3V3	current-sense output	3.3 V ±3%	250 mA	TP5
5V_BOOST	U4, disabled by default	5.0 V ±5%	150 mA	TP6
5V_TARGET	U5, disabled by default	5.0 V ±5%	100 mA	TP7

Sequence

Power J1 from a current-limited 5 V source at 100 mA with no battery. Stop on current limit, smoke, odor, or >60 °C hotspot.
Confirm USB_VBUS, VSYS, 3V3_PRE_SHUNT, and 3V3 in that order. Ripple target: <100 mVpp on 3V3 during boot.
Confirm 5V_BOOST, 5V_TARGET, and all switched 3.3 V rails remain off.
Raise the USB limit gradually to 500 mA only after stable rails are confirmed.
Repeat from Pack A only, Pack B only, then both packs. Remove one pack while operating and verify VBAT/VSYS do not reset or overshoot.
Operate each guarded isolation switch independently and verify only the selected pack is disconnected.
Attach the external 10 kΩ NTC to J11 before charge-current testing. Verify charger thermal regulation and charge status.

3. Boot, Reset, and Programming

SW3 NORMAL: reset with SW1 and confirm normal boot.
SW3 DOWNLOAD or SW2 held during SW1 reset: confirm esptool.py chip_id detects ESP32-S3.
Flash with pio run -t upload; verify 115200-baud diagnostics over native USB.
Confirm MCU_EN idles high and MCU_BOOT idles high in NORMAL mode.

4. Critical Interfaces

Table

Interface	Nets	Test
Native USB	USB_D_P, USB_D_N	Enumerate CDC, repeated connect/disconnect, check ESD array heating
I2C	I2C_SDA/IO8, I2C_SCL/IO9	Scan bus; confirm charger, gauge, monitors, TUSB320, U23 and U32
SPI backbone	SPI_CLK/IO12, SPI_MISO/IO13, SPI_MOSI/IO11	1 MHz logic-analyzer check before raising clock
UART0	UART_TX, UART_RX	115200 8N1 loopback at J8
microSD	J3, 3V3_SD_SW	Enable rail, verify card detect, initialize at low speed, read/write/verify 1 MB
Display	J6, 3V3_DISPLAY_SW	Enable rail and isolator, display color bars, test night mode and controls
NFC	J4, 3V3_NFC_SW	Enable only with module attached; read authorized test tag
Sub-GHz	J5, 3V3_SUBGHZ_SW	Receive test first; transmit only into legal test setup or shielded load
Protected target port	J7, VTGT	Verify no target power by default; test 1.8/3.3/5 V translation with current-limited fixture
Expansion	J8	Continuity, rail gating, bus loopback
Storage bay	J16, 3V3_STORAGE_SW	Presence detect, SPI loopback/read test, hot insertion only when firmware permits

5. Functional Blocks

Verify MAX17048 voltage and state-of-charge response.
Verify dual-pack voltage monitors, presence inputs, charger status inputs, and mux status through U31/U32.
Confirm every TPS22918 switched rail powers up and discharges down independently.
Check IR receive, then transmit into a nearby detector; limit LED duty cycle.
Verify microphone I2S capture and speaker amplifier at minimum volume before acoustic coupler testing.
Verify red-light/night mode does not unintentionally enable the main backlight.
Test buttons, boot selector, card detect, emergency isolation switches, and target-power fault reporting.
Confirm Wi-Fi scan and BLE advertising separately; keep NFC and sub-GHz disabled during baseline RF tests.

6. Thermal, Power, and Environmental Screening

Log USB-only, single-pack, and dual-pack current in idle, active UI, SD write, NFC, sub-GHz receive, and each controlled transmit state.
Run 30 minutes at worst-case intended load; no IC or connector should exceed its rated temperature and enclosure-touch surfaces should remain below 55 °C.
Verify deep sleep with all switched rails off and compare to the Phase 1 power budget.
After electrical pass, perform condensation-free cold/heat functional checks from -10 °C to +50 °C with battery operation restricted to the cell manufacturer's limits.
Splash testing is enclosure-level and must not be performed on an unsealed, energized PCB.

7. Pass/Fail Summary

Table

Section	Pass	Notes
Visual/unpowered	[ ]
USB and battery power	[ ]
Dual-pack hot swap/isolation	[ ]
3.3 V and switched rails	[ ]
Programming/boot controls	[ ]
USB/I2C/SPI/UART	[ ]
SD/display/UI	[ ]
NFC/sub-GHz/IR	[ ]
Protected target interface	[ ]
Audio/acoustic link	[ ]
Thermal and sleep power	[ ]

Board status: [ ] ready for controlled field prototype use [ ] requires rework

Prerequisites
1. Visual and Unpowered Inspection
2. Power Rail Verification
Sequence
3. Boot, Reset, and Programming
4. Critical Interfaces
5. Functional Blocks
6. Thermal, Power, and Environmental Screening
7. Pass/Fail Summary