Here’s what’s wrong (or missing) in the current wiring, based on your schematic and the live ERC/DRC results.
Top connectivity problems
- SPI between MCU and Wi‑Fi is miswired:
- IC1 PA4/SSI0RX is tied to U1 HOST_SPI_MOSI (RX should come from MISO, not MOSI).
- IC1 PA5/SSI0TX is tied to U1 FLASH_SPI_MISO (wrong bus and wrong direction; you should use U1’s HOST SPI, not FLASH SPI).
- SPI clock is unconnected: Net 1 has only IC1 PA2/SSI0CLK on it (single‑pin net).
- Chip select and IRQ are missing: U1 ~HOST_SPI_NCS and HOST_INTR have no connections to IC1.
- No power or ground networks are defined:
- None of the VDD/VSS/GND pins on IC1, U1, U2, or U3 are connected to rails or Ground symbols.
- No regulators, protection, or decoupling caps are present; net names are generic (“Net 1/2/3”) rather than explicit rails (e.g., 3V3, VMOTOR, USB_5V). The knowledge base emphasizes using clear power net names so ERC recognizes powered pins.
- I2C is not wired:
- IC1 PB2/I2C0SCL and PB3/I2C0SDA are not connected to U3 SCL/SDA.
- Required I2C pull‑ups are missing (knowledge base default is 4.7 kΩ) to the 3.3 V rail.
- Motor driver is completely unconnected:
- U2 VS, VSS, GND, ENA/ENB, IN1–IN4, SENSE_A/B, and OUT1–OUT4 are not tied to supplies, MCU GPIOs, or motor connectors.
- USB connector is not integrated:
- J1 VBUS, D+/D−, and GND are not connected to any rails, ESD/protection, or power-path inputs.
- No decoupling/bulk capacitors anywhere:
- Every IC lacks required local 100 nF decoupling (the knowledge base calls for a 100 nF ceramic within 5 mm per VCC/GND pair) and appropriate bulk caps per rail.
- SPI signal integrity parts are absent:
- Knowledge base recommends 22–33 Ω series resistors on high‑speed SPI lines; none are placed.
What the tools report right now
- DRC Airwires: open connections that need routing on the PCB
- IC1 PA4/SSI0RX ↔ U1 HOST_SPI_MOSI
- IC1 PA5/SSI0TX ↔ U1 FLASH_SPI_MISO
- ERC Single‑pin net exists (and Net 1 is visibly single‑pin at IC1:SSI0CLK). The knowledge base flags single‑pin nets and missing/undefined power rails as ERC risks.
SPI fix map (what each should connect to)
- IC1 PA5/SSI0TX (master MOSI) → U1 HOST_SPI_MOSI.
- IC1 PA4/SSI0RX (master MISO) ← U1 HOST_SPI_MISO.
- IC1 PA2/SSI0CLK → U1 HOST_SPI_CLK.
- IC1 GPIO (select one) → U1 ~HOST_SPI_NCS.
- IC1 GPIO (IRQ in) ← U1 HOST_INTR.
Immediate corrections to proceed
- Define rails and connect power/ground:
- Add explicit nets (e.g., 3V3, VMOTOR, USB_5V) and connect all VDD/VSS/GND pins using Ground symbols, per knowledge-base guidance on clear power naming.
- Add per‑IC decoupling (100 nF at each VDD pin) and bulk caps on each rail.
- Correct SPI per the “SPI fix map” above and add 22–33 Ω series resistors on CLK, MOSI, MISO (knowledge base practice).
- Wire I2C: IC1 PB2 ↔ U3 SCL, PB3 ↔ SDA, plus 4.7 kΩ pull‑ups to 3V3.
- Hook up U2 to VMOTOR and 3V3 logic, connect ENA/ENB and IN1–IN4 to MCU GPIOs, route OUT1–OUT4 to motor connectors, and connect SENSE_A/B appropriately.
- Integrate J1 into the power path and, if you intend USB data, add ESD and route D+/D−.
If you want, I can start fixing the schematic nets pin‑by‑pin. Tell me your intended power inputs (USB 5 V, battery, motor VS), and I’ll wire the rails, add decoupling and pull‑ups, and correct the SPI/I2C connections.