Analog

100 mm

0.655

U

Mono line-level AC-coupled audio on PA4 with EMI filtering via common-mode choke, ESD protection array, and RF shunt capacitor before J_AUD connector

100 mm

Coil Interface, TX Driver, RX Analog Front-End, Power Management, Mode Selection, Audio Stage, SWD Interface

Coil Interface: [], TX Driver: [], RX Analog Front-End: [], Power Management: [], Mode Selection: [], Audio Stage: [], SWD Interface: []

0.001 A

0.00322

0.625 A

VBAT high-current layout guidelines: 1. Connector and TVS placement - Keep J_BAT (282837-2) as the primary VBAT entry point feeding the TPS26600 (U7) IN pins. - Place D2 (SMBJ15A-13-F TVS) immediately adjacent to J_BAT on the VBAT side, with the shortest possible anode connection to GND and cathode to VBAT. - Avoid vias between J_BAT and D2; route on the same layer with a direct, low-inductance loop. 2. VBAT trace and polygon rules - Route VBAT from J_BAT Pin 1 to U7 IN pins using a wide copper trace or polygon on the top layer; minimum target width: - 2 oz Cu: ≥ 2.0–3.0 mm for primary VBAT segment. - Avoid narrow neck-downs in the VBAT path; any unavoidable necks should be as short as possible. - Prefer a solid VBAT polygon from J_BAT to U7, with clear keep-outs around sensitive analog/RX nodes. 3. Ground return and stitching - Use a solid ground plane (L2) under J_BAT, D2, and U7 to provide a low-impedance return path. - Add multiple GND stitching vias directly at: - J_BAT Pin 2 pad region. - D2 anode pad region. - U7 RTN/GND pins. - Target via count: at least 3–4 vias clustered near J_BAT Pin 2 and D2 anode, tying L1 copper to L2 GND. 4. Testpoint placement - Place TP_VBAT_IN on the VBAT copper between J_BAT Pin 1 and U7 IN, but not at the narrowest section of the trace; keep its connection as a short stub. - Place TP_GND close to J_BAT Pin 2 and share the same GND stitching region to minimize loop area when probing. 5. Inductance and loop area minimization - Minimize loop area of the VBAT surge path: J_BAT Pin 1 → VBAT copper → D2 cathode → D2 anode → GND plane → J_BAT Pin 2. - Keep this loop on the same layer (L1) above continuous GND (L2) and avoid routing over splits or cutouts. 6. Clearance and creepage - Maintain adequate clearance between VBAT copper and any low-voltage/logic nets, targeting ≥ 0.5 mm where practical. - Keep analog/RX front-end traces away from the J_BAT/VBAT region by at least 10 mm on L1; if crossing is unavoidable, prefer inner layers with strong GND shielding. 7. Future layout checks - During DRC review, explicitly verify: (a) VBAT trace width, (b) presence of multiple GND stitching vias near J_BAT/D2/U7, (c) short TVS connection, and (d) absence of plane splits in the VBAT/GND surge loop region.

LQFP-64_L10.0-W10.0-P0.50-LS12.0-BL

Coupling

Protection

Connector

Extended Part

0.003

0.002 A

0.00022 A

6-layer stackup (2 oz outer, 1 oz inner) layout checklist: 1. Stackup assumptions - L1: Top signal (primary for MCU, TX, RX, audio, and coil interface) - L2: Solid GND reference plane (continuous under all high-speed / high-di/dt nets, DAC/AUDIO, TX, RX) - L3: Inner signal 1 (low-noise analog / RX inner routing when needed) - L4: Inner signal 2 (digital / control / interface) - L5: Solid power plane(s) or split power (3V3, 5V, TX drive rail) with strict return-path planning to L2 - L6: Bottom signal (slower signals, local pours, stitching vias to L2 GND) 2. Coil / TX driver placement rules - Place TX MOSFETs, TX driver, and TX return loop tightly coupled, as close to the coil connector as mechanically allowed. - Minimize loop area for TX current path (TX driver -> coil+ -> coil- -> return). - Route primary TX current loop on L1 (and optionally L6) directly over solid GND on L2; avoid routing TX over plane splits. - Keep any sensitive analog/RX traces and components at least 10 mm away from TX high-di/dt copper (including polygons). - Avoid any vias in the main TX current loop except where absolutely required for connector breakout. 3. RX analog front-end placement rules - Place RX front-end (low-noise amps, integrators, filters) close together with shortest possible feedback loops. - Keep RX input traces away from TX copper and digital clocks by at least 10 mm; prefer L1 routing over solid L2 GND. - Do not route RX inputs or high-impedance nodes parallel to TX traces for more than 5 mm; cross at 90° if crossing is unavoidable. - Keep all RX input and feedback routing on a single layer where possible to avoid via stubs; when vias are required, use adjacent GND stitching vias. 4. Coil / TX / RX keep-out rules - Define a coil keep-out region around the coil connector and TX current loop where no sensitive analog or digital traces may pass (minimum radius 15–20 mm from coil connector center, adjust to mechanical constraints). - Inside the coil keep-out, only allow: TX copper, coil connector pins, TX sense resistors/shunts, and local GND stitching vias. - Define an RX keep-out region excluding TX polygons, high-current power traces, and switching nodes from entering within 10 mm of RX inputs. - Prohibit placing high di/dt switching nodes (TX drain, flyback nodes, DC-DC switch nodes) under or directly adjacent to the RX analog section. 5. Via stitching templates - Around the coil connector and TX loop, place a ring of GND stitching vias tying L1/L6 pours to L2 GND every 2.0–2.5 mm along the perimeter. - Along the boundary between TX region and RX analog region, place a GND via fence (L1 to L2 to L6) on 2.0–2.5 mm pitch forming an EMI barrier. - Around sensitive RX analog input traces that must run near TX or digital regions, place paired GND stitching vias every 3–4 mm along both sides of the trace where geometry permits. - Stitch all local GND copper used for shielding (on L1 and L6) down to the solid GND plane (L2) with vias every 3–4 mm. 6. Audio output (PA4) routing notes - Route AUDIO_MONO_OUT as a short, single-ended trace on L1 over continuous L2 GND from PA4 -> R_SERIES -> C_AC -> L_CHOKE -> U_ESD -> C_RF -> J_AUD. - Keep the total PA4-to-connector length as short as practical, target < 30–40 mm if mechanically possible. - Avoid routing AUDIO_MONO_OUT parallel to TX traces or clock lines for more than 5–10 mm; cross at 90° when crossing is needed. - Place at least one GND stitching via near each of R_SERIES, C_AC, L_CHOKE, U_ESD, and C_RF tying top copper pours to L2 GND. 7. General placement and routing hygiene - Maintain continuous GND beneath all high-speed or high-di/dt nets; avoid slots, voids, or plane cuts under TX, RX, and AUDIO. - Keep decoupling capacitors for TX drivers, MCU, and RX amplifiers as close as possible to their supply pins with direct, short return paths to L2 GND. - Avoid long, narrow necked copper sections on GND in TX, RX, and audio regions; keep GND pours wide and well-stitched. - Reserve mechanical keep-out for enclosures and coil cabling so that TX and RX placement is not compromised late in the design.

STM32G474RET6

```mermaid flowchart TD A["TPS54331DR Buck Converter"] --> B["Buck Support Network"] C["TPS26600 eFuse"] --> D["UVLO/OVP/ILIM/dVdT Network"] C --> E["IMON Testpoint"] F["J_ONOFF Header"] --> G["Series Resistor R6"] G --> H["EN Chain"] H --> Z["U7 EN Pin"] H --> I["Pull-Up Resistor R7"] H --> J["RC Capacitor C8"] H --> K["ESD Diode D3"] H --> L["TP_EN Testpoint"] M["PA4 MCU Pin"] --> N["Series Resistor"] N --> O["AC Coupling Cap C_AC"] O --> P["Choke L_CHOKE"] P --> Q["ESD Array U_ESD"] Q --> R["RF Cap C_RF"] R --> S["J_AUD Connector"] T["MOSFET Gate Node"] --> U["Gate Pull-Down R_pd"] T --> V["VGS TVS"] W["CSA_BLANK_CTRL Net"] --> X["Blanking Switch U6"] X --> Y["ADC Path"] ```

Coil / TX / RX keep-out and via stitching templates: 1. Coil keep-out region - Define a coil keep-out region around the coil connector and primary TX current loop. - Target radius: **15–20 mm** from the coil connector center, adjusted only as required by mechanical constraints. - Inside this coil keep-out region, only allow: - TX copper (current-carrying traces and polygons for the TX loop). - Coil connector pins and their immediate breakout. - TX sense resistors / shunts directly in the main TX loop. - Local GND stitching vias tying surface copper to the solid GND plane. - Do not route any sensitive analog, digital, or audio traces through this region. 2. RX keep-out region - Define an RX input / analog keep-out boundary around all RX front-end inputs and high-impedance nodes. - Keep TX polygons, high-current power traces, and all high di/dt switching nodes (TX drain, flyback nodes, DC-DC switch nodes) **at least 10 mm** away from RX input pins and their immediate routing. - Do not place switching converters or TX driver components under or directly adjacent to the RX analog section. - Prefer RX signal routing on L1 over a continuous L2 GND plane; avoid crossing any plane splits inside the RX region. 3. Via stitching templates 3.1 Coil / TX loop via ring - Around the coil connector footprint and the main TX current loop, place a ring of GND stitching vias to tie: L1 GND pour -> L2 solid GND plane -> L6 GND pour. - Target via pitch: **2.0–2.5 mm** along the perimeter of the coil / TX region. - Place vias just outside the primary TX current copper to minimize loop area while maintaining clearances. 3.2 TX-to-RX boundary via fence - Along the logical boundary between the TX region and the RX analog region, place a linear GND via fence. - Each via should connect L1, L2, and L6 (and any other GND-carrying internal layers if present). - Target via pitch: **2.0–2.5 mm** along the entire boundary. - Use this fence as an EMI barrier; do not leave large gaps or breaks in the fence in areas where TX and RX copper approach each other. 3.3 RX trace-side stitching - For sensitive RX analog traces that must run near TX or digital regions, place paired GND stitching vias on both sides of the trace where geometry allows. - Target spacing: **3–4 mm** between via pairs along the trace length. - Tie all such stitching vias to the solid L2 GND plane and any local L1/L6 GND pours. 3.4 General GND pour stitching - Any local GND copper used for shielding on L1 or L6 must be stitched down to L2 GND with vias every **3–4 mm**. - Avoid long, unstitched GND “islands”; prefer continuous, well-connected GND pours for TX, RX, and audio regions. 4. Audio routing reference (for context) - Route AUDIO_MONO_OUT on L1 above continuous L2 GND, keeping it away from TX loops and high di/dt nodes, using local GND stitching vias near key audio components and at transitions between regions.

Panel-mounted J_ONOFF header drives TPS26600 (U7) EN pin through 10 kΩ series resistor, with 100 kΩ pull-up to VBAT, 100 nF RC to RTN for debounce and stability, and low-capacitance ESD diode from EN to RTN for surge and ESD protection on the user-accessible power switch interface.

Circular Connectors

6 layers (2 oz outer, 1 oz inner)

0.043 A

0.03 A