Concise Part Description Request

jharwinbarrozo

jharwinbarrozo

Update the project description with this concise text, then verify the BOM attributes match the datasheet.

flux

I’ll update the project description to the concise datasheet-based text, then inspect the BOM attributes against the part’s datasheet details.

flux

Updated the project description with the concise datasheet-based text.
Verification result:
  • BOM: No BOM parts are currently added, so there are no BOM attributes to validate.
  • Schematic/part model: The project contains 224 terminal entries, consistent with the project’s listed pad count.
  • Part-review checks: No matching component-review issues were returned.
Open item:
  • If you want BOM attributes verified, the FPGA needs to exist as a proper BOM component entry, not only as terminal symbols.
Create BOM component
Add FPGA component
Verify pin mapping
Add missing attributes
Run schematic review
IO/DIFFIO_T22n
IO/DIFFIO_B18n
GND
IO/INIT_DONE/DIFFIO_R5n
IO/DIFFIO_B2n
VCCINT
Pin Number
G7
IO/DPCLK3/DIFFIO_B8n
MSEL1
IO/CRC_ERROR/DIFFIO_R5p
IO/DIFFIO_L13p
CLK7/DIFFCLK_3n
IO/DIFFIO_L6n
CLK13/DIFFCLK_7p
IO/DIFFIO_T5p
GND
GND
IO/DATA0
IO/DIFFIO_T9n
IO/DIFFIO_R8n
VCCD_PLL4
VCCIO7
Pin Number
C13
IO/DIFFIO_B20n
IO/DATA3/DIFFIO_T10p
IO/PLL2_CLKOUTp
VCCINT
Pin Number
M9
nCONFIG
IO/DIFFIO_B4p
VCCINT
Pin Number
K7
IO/DIFFIO_B6n
IO/DPCLK0/DIFFIO_L6p
GND
IO/DATA1/ASDO/DIFFIO_L3n
IO/PLL1_CLKOUTp
VCCA4
GND
IO/DIFFIO_B7n
CLK11/DIFFCLK_4p
GND
GND
GND
TMS
GND
IO/DPCLK2/DIFFIO_B5p
IO/DATA3/DIFFIO_T10p
IO/DIFFIO_B6p
IO/DPCLK6/DIFFIO_R10p
VCCIO2
Pin Number
M3
GND
TDI
IO/CDPCLK3/DIFFIO_B23n
VCCA1
GND
GND
VCCIO2
CLK9/DIFFCLK_5p
IO/DIFFIO_B1p
CLK12/DIFFCLK_7n
GND
IO/DIFFIO_T2n
IO/DIFFIO_B17n
VCCIO5
GND
IO/DIFFIO_T24n
GND
IO/DIFFIO_R13p
IO/RDN2
VCCIO6
CLK4/DIFFCLK_2p
TCK
IO/RUP4
IO/DIFFIO_T2p
IO
IO/DPCLK9/DIFFIO_T13p
CLK10/DIFFCLK_4n
IO/DIFFIO_R11n
IO/RDN3
GND
IO/DIFFIO_L13n
VCCIO3
Pin Number
T1
IO/DIFFIO_L15n
IO/DIFFIO_B20p
GND
IO/DIFFIO_L15p
IO
Pin Number
D8
IO/DEV_OE/DIFFIO_R9n
GND
IO/RUP3
GND
IO/DIFFIO_R13n
IO/DIFFIO_T20n
IO/DATA4/DIFFIO_T9p
GND
MSEL0
IO/DATA7/DIFFIO_T5n
IO/DIFFIO_B16p
VCCINT
GND
CLK3/DIFFCLK_1n
IO/DIFFIO_R7n
VCCINT
Pin Number
K11
IO/DIFFIO_T7p
IO/PLL3_CLKOUTp
IO/PLL1_CLKOUTn
IO/DIFFIO_B23p
IO/PLL3_CLKOUTn
VCCIO4
CLK15/DIFFCLK_6p
IO/DIFFIO_T3p
IO/DIFFIO_B14n
GND
VCCINT
Pin Number
H11
IO/CLKUSR/DIFFIO_R4p
nSTATUS
VCCINT
Pin Number
M11
IO/DIFFIO_T3n
IO/DIFFIO_T19n
VCCINT
Pin Number
G9
IO/DIFFIO_T24n
IO/VREFB7N0
VCCA3
GND
IO/DPCLK10/DIFFIO_T11p
IO/DIFFIO_L3p
IO/DPCLK1/DIFFIO_L11p
IO
Pin Number
D16
VCCD_PLL1
IO/DIFFIO_B17p
IO/RUP1
VCCINT
Pin Number
H6
GND
GND
GNDA2
IO/DIFFIO_B11p
GND
VCCIO3
GND
GND
MSEL2
VCCINT
Pin Number
K10
IO/PLL4_CLKOUTp
IO/DIFFIO_R10n
IO/RUP2
IO/DIFFIO_L7n
CLK2/DIFFCLK_1p
nCE
VCCA2
IO/DIFFIO_B8p
VCCIO7
Pin Number
C10
VCCINT
Pin Number
F11
IO/DIFFIO_T23n
GND
VCCD_PLL3
IO/DIFFIO_T15n
IO/DIFFIO_B12n
IO/DCLK
IO
IO/DIFFIO_B2p
VCCIO4
Pin Number
P13
IO/DIFFIO_T16n
IO/DIFFIO_T22p
GND
IO/DIFFIO_L11n
CLK0/DIFFCLK_0p
CONF_DONE
VCCINT
Pin Number
J6
IO/DEV_CLRn/DIFFIO_R9p
IO/CDPCLK5/DIFFIO_R1n
IO/DIFFIO_B9n
IO/VREFB5N0
GND
GND
GND
GNDA1
IO/DIFFIO_T15p
GND
VCCINT
Pin Number
L6
IO/DIFFIO_B18p
IO/VREFB4N0
VCCINT
Pin Number
J12
VCCINT
Pin Number
G10
VCCCIO8
Pin Number
C7
IO/VREFB2N0
IO/VREFB1N0
VCCIO5
Pin Number
M14
IO/CDPCLK0
GNDA3
GND
IO/VREFB3N0
IO/DIFFIO_B1n
IO/DIFFIO_T16p
IO/RDN1
IO/VREFB6N0
IO/DIFFIO_T20p
IO/CDPCLK2
VCCINT
Pin Number
G8
IO/DIFFIO_B10n
TDO
VCCIO3
Pin Number
P7
IO/CDPCLK1
GND
VCCIO8
IO
Pin Number
D15
VCCCIO8
Pin Number
C4
IO/DPCLK5
IO/DIFFIO_B4n
IO/DIFFIO_B7p
CLK10/DIFFCLK_4n
IO/DIFFIO_T21n
IO/FLASH_nCE/nCSO/DIFFIO_L4p
IO/DIFFIO_T22n
VCCINT
Pin Number
G6
IO/DATA6/DIFFIO_T6p
IO/DIFFIO_L7p
IO/VREFB8N0
IO/DIFFIO_L10n
IO/DATA5
IO/DIFFIO_B24p
IO/DIFFIO_R12p
CLK14/DIFFCLK_6n
IO/DIFFIO_L4n
GND
CLK1/DIFFCLK_0n
VCCIO4
Pin Number
T16
IO/DIFFIO_T24p
GND
GND
IO/DPCLK7
GND
IO/CDPCLK7
CLK4/DIFFCLK_2p
IO/DATA5
IO/nCEO/DIFFIO_R4n
VCCIO1
Pin Number
G3
GND
IO/DATA7/DIFFIO_T5n
IO/RDN4
IO/DIFFIO_T23n
IO/CDPCLK4/DIFFIO_R15n
IO/DIFFIO_R15p
IO/PLL4_CLKOUTn
GNDA4
VCCIO6
Pin Number
G14
VCCINT
Pin Number
K9
IO/DIFFIO_T21p
IO/DIFFIO_L10p
VCCD_PLL2
IO/DIFFIO_T19n
IO/DPCLK4/DIFFIO_B16n
IO
GND
GND
CLK6/DIFFCLK_3p
IO/PLL3_CLKOUTp
VCCIO1
GND
IO/DIFFIO_R11p

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Part Review — Intel/Altera 10CL025YU256I7G
Sources reviewed
  • Current Flux part project metadata and properties
  • Current schematic symbol terminals and terminal properties
  • Current PCB footprint summary
  • Official Intel/Altera product and documentation sources:
    • Product page: https://www.altera.com/products/fpga/cyclone/10/lp/10cl025-u256/10CL025YU256I7G
    • Intel Cyclone 10 LP Device Datasheet, document ID 683251
    • Intel Cyclone 10 10CL025 Pin Information PDF/XLS, document IDs 657005 / 656892
    • Official pin information PDF content URL: https://cdrdv2-public.intel.com/657005/10cl025.pdf
    • Intel Cyclone 10 Package Mechanical Drawings, document ID 682731
Current part metadata

Table

FieldCurrent value
MPN10CL025YU256I7G
ManufacturerIntel/Altera
LCSC PNC1521864
Part typeCPLD/FPGA
Designator prefixU
Package/caseFBGA-256_L14.0-W14.0-R16-C16-P0.80-TL
Symbol styleparametric-v1
Pin/terminal count256 terminals
Datasheet URLAlready set: https://docs.altera.com/viewer/book-attachment/_PQecBN7YCFyCsTJRrWoHQ/17dUYtHQ~o~BQSNGFUaQgw-_PQecBN7YCFyCsTJRrWoHQ
Because a datasheet URL was already present, I did not overwrite it. The URL is an Altera docs URL, but for long-term traceability I recommend adding or changing it to the canonical Intel pin-information PDF URL (https://cdrdv2-public.intel.com/657005/10cl025.pdf) or the Intel document landing page.
Key official specs

Table

SpecDatasheet / official value
FamilyIntel/Altera Cyclone 10 LP FPGA
Device10CL025
Ordering part number10CL025YU256I7G
LifecycleIn production
Logic elements24,624 / marketed as 25K
LABs / CLBs1,539
Embedded RAM594 Kb / 608,256 bits
M9K blocks66
18 × 18 multipliers66
PLLs4
Max user I/O150
U256 LVDS channels52
Core voltage1.2 V nominal; VCCINT 1.15–1.25 V recommended operating range
Temperature gradeIndustrial, TJ = -40°C to +100°C
Speed grade7
RoHS codeG = RoHS6 compliant
Package256-pin Ultra FineLine UBGA / 256-LFBGA
Package size14 mm × 14 mm
Ball pitch0.8 mm
Shipping mediaTray
MSL / floor lifeMSL 3, 168 h at ≤30°C/60% RH
Symbol / pin cross-check
What matches
  • Project has exactly 256 schematic terminals, matching the official 256-ball U256 package.
  • JTAG/configuration balls checked against the official pin list match:
    • TCK = H3
    • TMS = J5
    • TDI = H4
    • TDO = J4
    • nCONFIG = H5
    • CONF_DONE = H14
  • Power pin groups sampled against the official pin list match for many entries:
    • VCCINT includes F7, F11, G6, G7, G8, G9, G10, H6, H11, J6, K7, K11, L6, K9, K10, M9, M11, J12
    • VCCA1/2/3/4 = L5/F12/F5/L12
    • GNDA1/2/3/4 = M5/E12/E5/M12
    • VCCD_PLL1/2/3/4 = N4/D13/D4/N13
    • VCCIO bank pins checked match the official bank list, except for the typo noted below.
Mismatches / issues flagged
  1. Several terminals appear to have ball/function fields reversed.
    Examples from the current symbol:
    • G16 has Pin Number = IO/INIT_DONE/DIFFIO_R5n; official format should be ball G16 with function IO / INIT_DONE / DIFFIO_R5n.
    • H12 has Pin Number = MSEL1/MSEL1; official ball is H12, function MSEL1.
    • H13 has Pin Number = MSEL0/MSEL0; official ball is H13, function MSEL0.
    • M16 has Pin Number = CLK7/DIFFCLK_3n; official ball is M16, function CLK7 / DIFFCLK_3n.
    • J14 has Pin Number = IO/DIFFIO_R8n; official ball is J14, function IO / DIFFIO_R8n.
    • N13, F7, L12, K3, K14, and E14 are also represented as designator=ball with Pin Number=function instead of designator/function with Pin Number=ball.
  2. Typo in VCCIO8 terminal label: current symbol contains VCCCIO8; official spelling is VCCIO8. Official U256 VCCIO8 balls are A1, C4, C7.
  3. Pin Type is mostly Unspecified.
    For a part-quality symbol, power pins should be Power/Ground or equivalent, JTAG/configuration pins should be input/output as appropriate, and user I/O pins should be bidirectional/I/O. This is not necessarily a pinout mismatch, but it weakens ERC quality.
  4. Pin descriptions are not consistently separated from pin numbers.
    Many terminals use the symbol designator as the pin function and Pin Number as the ball, which is good. Others use the ball as the designator and the function as Pin Number, which will make schematic usage and footprint mapping error-prone.
Footprint cross-check

Table

ItemCurrent projectOfficial requirementResult
PCB pads256256 ballsPass
Package size property14.0 mm × 14.0 mm14 mm × 14 mmPass
Array propertyR16-C1616 × 16 ball arrayPass
Pitch property0.80 mm0.8 mmPass
Package typeFBGA/UBGA-256256-pin UBGA / 256-LFBGAPass
The layout summary shows 256 pad nodes plus footprint/container/text/line metadata. That matches the official 256-ball package at a summary level. I did not verify every pad coordinate against the mechanical drawing in this pass because the layout tree output did not expose pad geometry details in the summary view.
  1. Normalize every terminal so Pin Number is always the physical U256 ball coordinate and the visible terminal label/designator is the signal/function name.
  2. Rename VCCCIO8 terminals to VCCIO8.
  3. Add explicit Pin Description for terminals using official pin information fields: primary pin name, optional function, configuration function, bank, VREF group, and LVDS channel where applicable.
  4. Assign meaningful Pin Type values rather than leaving all pins Unspecified.
  5. Consider replacing the Datasheet URL with the canonical Intel pin-information PDF or adding it as an additional reference URL if the current Altera attachment URL is retained.

  • Sources reviewed

  • Current part metadata

  • Key official specs

  • Symbol / pin cross-check

  • What matches

  • Mismatches / issues flagged

  • Footprint cross-check

  • Recommended fixes

Documents

Assets

10CL025YU256I7G/10CL025YU256I7G.pretty/FBGA-256_L14.0-W14.0-R16-C16-P0.80-TL.kicad_mod

10CL025YU256I7G/10CL025YU256I7G FootprintFootprint
10CL025YU256I7G.stp

10CL025YU256I7G.stp

10CL025YU256I7G3D Model
10CL025YU256I7G-thumb.png

10CL025YU256I7G-thumb.png

10CL025YU256I7G-thumbThumbnail

10CL025YU256I7G

10CL025YU256I7G thumbnail
Intel/Altera 10CL025YU256I7G is a Cyclone 10 LP low-power FPGA in a 256-ball UBGA, 14 × 14 mm package, offering 24,624 logic elements, 150 user I/Os, 594 Kb embedded RAM, 66 embedded 18×18 multipliers, and 4 PLLs. It uses a 1.2 V core, supports industrial operation from -40°C to 100°C TJ, and is intended for cost-sensitive embedded logic, I/O expansion, signal processing, and control applications.

Properties

10CL025YU256I7G

Intel/Altera

CPLD/FPGA

docs.altera.com/viewer/book-attachment/_PQecBN7YCFyCsTJRrWoHQ/17dUYtHQ~o~BQSNGFUaQgw-_PQecBN7YCFyCsTJRrWoHQ

U

C1521864

FBGA-256_L14.0-W14.0-R16-C16-P0.80-TL

Extended Part

parametric-v1

Pricing & Availability

DPN

Stock

Qty 1

2

0

$26.68

1

29

$21.4681

1

0

$32.62

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