Concise Part Description Request

Thought for 12 sec

I’ll verify the part identity and pull the key datasheet-level attributes, then give you a concise usable description.

Worked for 1 min 3 sec

Intel/Altera 10CL025YU256I7G is a Cyclone 10 LP low-power FPGA in a 256-ball UBGA, 14 × 14 mm package, offering 24,624 logic elements, 150 user I/Os, 594 Kb embedded RAM, 66 embedded 18×18 multipliers, and 4 PLLs. It uses a 1.2 V core, supports industrial operation from -40°C to 100°C TJ, and is intended for cost-sensitive embedded logic, I/O expansion, signal processing, and control applications.

jharwinbarrozo

Update the project description with this concise text, then verify the BOM attributes match the datasheet.

Thought for 14 sec

flux

I’ll update the project description to the concise datasheet-based text, then inspect the BOM attributes against the part’s datasheet details.

Worked for 1 min 25 sec

flux

Updated the project description with the concise datasheet-based text.

Verification result:

BOM: No BOM parts are currently added, so there are no BOM attributes to validate.
Schematic/part model: The project contains 224 terminal entries, consistent with the project’s listed pad count.
Part-review checks: No matching component-review issues were returned.

Open item:

If you want BOM attributes verified, the FPGA needs to exist as a proper BOM component entry, not only as terminal symbols.

Create BOM component

Add FPGA component

Verify pin mapping

Add missing attributes

Run schematic review

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Part Review — Intel/Altera 10CL025YU256I7G

Sources reviewed

Current Flux part project metadata and properties
Current schematic symbol terminals and terminal properties
Current PCB footprint summary
Official Intel/Altera product and documentation sources:
- Product page: https://www.altera.com/products/fpga/cyclone/10/lp/10cl025-u256/10CL025YU256I7G
- Intel Cyclone 10 LP Device Datasheet, document ID 683251
- Intel Cyclone 10 10CL025 Pin Information PDF/XLS, document IDs 657005 / 656892
- Official pin information PDF content URL: https://cdrdv2-public.intel.com/657005/10cl025.pdf
- Intel Cyclone 10 Package Mechanical Drawings, document ID 682731

Current part metadata

Table

Field	Current value
MPN	10CL025YU256I7G
Manufacturer	Intel/Altera
LCSC PN	C1521864
Part type	CPLD/FPGA
Designator prefix	U
Package/case	FBGA-256_L14.0-W14.0-R16-C16-P0.80-TL
Symbol style	parametric-v1
Pin/terminal count	256 terminals
Datasheet URL	Already set: `https://docs.altera.com/viewer/book-attachment/_PQecBN7YCFyCsTJRrWoHQ/17dUYtHQ~o~BQSNGFUaQgw-_PQecBN7YCFyCsTJRrWoHQ`

Because a datasheet URL was already present, I did not overwrite it. The URL is an Altera docs URL, but for long-term traceability I recommend adding or changing it to the canonical Intel pin-information PDF URL (https://cdrdv2-public.intel.com/657005/10cl025.pdf) or the Intel document landing page.

Key official specs

Table

Spec	Datasheet / official value
Family	Intel/Altera Cyclone 10 LP FPGA
Device	10CL025
Ordering part number	10CL025YU256I7G
Lifecycle	In production
Logic elements	24,624 / marketed as 25K
LABs / CLBs	1,539
Embedded RAM	594 Kb / 608,256 bits
M9K blocks	66
18 × 18 multipliers	66
PLLs	4
Max user I/O	150
U256 LVDS channels	52
Core voltage	1.2 V nominal; VCCINT 1.15–1.25 V recommended operating range
Temperature grade	Industrial, TJ = -40°C to +100°C
Speed grade	7
RoHS code	G = RoHS6 compliant
Package	256-pin Ultra FineLine UBGA / 256-LFBGA
Package size	14 mm × 14 mm
Ball pitch	0.8 mm
Shipping media	Tray
MSL / floor life	MSL 3, 168 h at ≤30°C/60% RH

Symbol / pin cross-check

What matches

Project has exactly 256 schematic terminals, matching the official 256-ball U256 package.
JTAG/configuration balls checked against the official pin list match:
- TCK = H3
- TMS = J5
- TDI = H4
- TDO = J4
- nCONFIG = H5
- CONF_DONE = H14
Power pin groups sampled against the official pin list match for many entries:
- VCCINT includes F7, F11, G6, G7, G8, G9, G10, H6, H11, J6, K7, K11, L6, K9, K10, M9, M11, J12
- VCCA1/2/3/4 = L5/F12/F5/L12
- GNDA1/2/3/4 = M5/E12/E5/M12
- VCCD_PLL1/2/3/4 = N4/D13/D4/N13
- VCCIO bank pins checked match the official bank list, except for the typo noted below.

Mismatches / issues flagged

Several terminals appear to have ball/function fields reversed.
Examples from the current symbol:
- G16 has Pin Number = IO/INIT_DONE/DIFFIO_R5n; official format should be ball G16 with function IO / INIT_DONE / DIFFIO_R5n.
- H12 has Pin Number = MSEL1/MSEL1; official ball is H12, function MSEL1.
- H13 has Pin Number = MSEL0/MSEL0; official ball is H13, function MSEL0.
- M16 has Pin Number = CLK7/DIFFCLK_3n; official ball is M16, function CLK7 / DIFFCLK_3n.
- J14 has Pin Number = IO/DIFFIO_R8n; official ball is J14, function IO / DIFFIO_R8n.
- N13, F7, L12, K3, K14, and E14 are also represented as designator=ball with Pin Number=function instead of designator/function with Pin Number=ball.
Typo in VCCIO8 terminal label: current symbol contains VCCCIO8; official spelling is VCCIO8. Official U256 VCCIO8 balls are A1, C4, C7.
Pin Type is mostly Unspecified.
For a part-quality symbol, power pins should be Power/Ground or equivalent, JTAG/configuration pins should be input/output as appropriate, and user I/O pins should be bidirectional/I/O. This is not necessarily a pinout mismatch, but it weakens ERC quality.
Pin descriptions are not consistently separated from pin numbers.
Many terminals use the symbol designator as the pin function and Pin Number as the ball, which is good. Others use the ball as the designator and the function as Pin Number, which will make schematic usage and footprint mapping error-prone.

Footprint cross-check

Table

Item	Current project	Official requirement	Result
PCB pads	256	256 balls	Pass
Package size property	14.0 mm × 14.0 mm	14 mm × 14 mm	Pass
Array property	R16-C16	16 × 16 ball array	Pass
Pitch property	0.80 mm	0.8 mm	Pass
Package type	FBGA/UBGA-256	256-pin UBGA / 256-LFBGA	Pass

The layout summary shows 256 pad nodes plus footprint/container/text/line metadata. That matches the official 256-ball package at a summary level. I did not verify every pad coordinate against the mechanical drawing in this pass because the layout tree output did not expose pad geometry details in the summary view.

Recommended fixes

Normalize every terminal so Pin Number is always the physical U256 ball coordinate and the visible terminal label/designator is the signal/function name.
Rename VCCCIO8 terminals to VCCIO8.
Add explicit Pin Description for terminals using official pin information fields: primary pin name, optional function, configuration function, bank, VREF group, and LVDS channel where applicable.
Assign meaningful Pin Type values rather than leaving all pins Unspecified.
Consider replacing the Datasheet URL with the canonical Intel pin-information PDF or adding it as an additional reference URL if the current Altera attachment URL is retained.

Sources reviewed
Current part metadata
Key official specs
Symbol / pin cross-check
What matches
Mismatches / issues flagged
Footprint cross-check
Recommended fixes