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#Goal

- Modify the current circular Ø73 mm PCB design to incorporate a bottom-side heatsink keep-out area, ensuring that all connectors and small-signal parts remain on the top side while relocating the power MOSFETs (Q1/Q2) to the bottom side over the designated heatsink area with symmetric M3 NPTH mounting and proper clearances. Finally, validate the design with a DRC check.

#Implementation plan

1. Define the bottom-side heatsink keep-out area:

1. Create a circular keep-out zone on the bottom layer, centering it on the board with a diameter of 38 mm (or other agreed dimension) to serve as the heatsink area.

2. Lock this keep-out zone to the bottom copper/component/via layers only.

2. Prepare and position the mounting holes:

1. Locate M3 NPTH mounting holes (Hole5, Hole6) and position them symmetrically about the board center.

2. Apply a 1.5 mm copper keep-out around each M3 NPTH hole to ensure proper clearance.

3. Relocate power MOSFETs (Q1 and Q2):

1. Move Q1 and Q2 from the top layer to the bottom side, aligning them over the designated heatsink keep-out area.

2. Establish tight thermal-via fences around the keep-out for optimum heat dissipation and to connect to L2 (GND) as needed.

4. Retain other critical components on the top side:

1. Ensure all connectors (e.g., J1–J4) and small signal parts remain exclusively on the top side.

2. Verify that short high di/dt loops and proper ground returns are maintained.

5. Validate design through DRC:

1. Run a complete DRC check to confirm that all clearances, keep-out zones, mounting requirements, and positional constraints are met.

2. Adjust placements if any DRC errors are detected to ensure manufacturability.

#Success criteria

- The bottom-side heatsink keep-out is correctly defined and locked to the appropriate layers on a Ø73 mm circular PCB.

- M3 NPTH mounting holes for Q1/Q2 are symmetrically positioned with a proper 1.5 mm clearance keep-out.

- Q1 and Q2 are successfully relocated to the bottom layer over the heatsink area with effective thermal management implemented (e.g. thermal via fences).

- Connectors and all small-signal components remain on the top side, maintaining short high di/dt loops and clean ground returns.

- The final design passes the DRC with no clearance or placement violations.

flux

#Goal

- Modify the existing Ø73 mm circular PCB for the Desirable Apricot Holodeck by adding a bottom-side heatsink keep-out area, relocating the power MOSFETs (Q1/Q2) to the bottom over the designated area, and maintaining all connectors and small-signal parts (J1–J4 and others) on the top. Validate the layout via DRC to ensure design rule compliance.

#Implementation plan

1. Define heatsink keep-out zone on the bottom layer:

1. Create a centered circular keep-out region (Ø38 mm) on the bottom layer that prevents copper, vias, and component placement within the heatsink area.

2. Lock the keep-out to affect only the bottom layer.

2. Update NPTH hole placement for symmetric mounting:

1. Position NPTH holes Hole5 and Hole6 symmetrically around the board center.

2. Add a 1.5 mm copper keep-out or clearance ring around each of these holes to avoid interference with the bottom heatsink area.

3. Relocate power MOSFETs:

1. Move Q1 and Q2 (IPT012N08N5) to the bottom side, positioning them over the defined heatsink keep-out zone.

2. Add a dense thermal via fence around the perimeter of the keep-out area, connecting to the bottom layer GND (L2), to enhance thermal performance.

4. Maintain connectors and small-signal components on the top side:

1. Ensure that J1–J4 (282837-2 and 0022232031) and small-signal parts (e.g., U2 INA180A1, U5 LM393ADR, other passive components) remain on the top layer.

2. Verify that power supply routing and high di/dt loops remain short, as per design requirements.

5. Run DRC validation:

1. Execute a Design Rule Check (DRC) to identify and resolve any clearance or placement violations due to the modifications.

#Success criteria

- The bottom layer features a clearly defined Ø38 mm keep-out area for the heatsink that blocks copper, vias, and components.

- Power MOSFETs Q1/Q2 are relocated to the bottom layer and positioned over the heatsink keep-out, with an adjacent thermal via fence tied to GND.

- All connectors and small-signal components remain exclusively on the top layer.

- DRC results show no rule violations related to clearance, component placement, or keep-out conflicts.