• Form factor: M.2 3052
• Board size: 52.0 mm x 30.0 mm
• Architecture:
  • connector / power / FPGA at the M.2 end
  • 2x AD9363 in the RFIC band
  • 4 receive lanes at the far edge
• Objective:
  • preserve matched receive path geometry
  • preserve equivalent local support around both AD9363 devices
  • avoid ad hoc routing changes that break lane-to-lane symmetry

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• Origin: lower-left corner
• X axis: 0.0 mm to 52.0 mm
• Y axis: 0.0 mm to 30.0 mm
• Symmetry reference line: Y = 15.0 mm

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• Same X center for both AD9363: 32.0 mm
• Mirrored about Y = 15.0 mm
• Center-to-center Y spacing: 14.0 mm
• Rotation mismatch allowed: 0 deg
• X placement mismatch allowed: <= 0.10 mm
• Y symmetry mismatch allowed: <= 0.10 mm

• ☐ RFIC X centers match
• ☐ RFIC Y positions are mirrored
• ☐ RFIC orientations are equivalent
• ☐ RFIC digital sides face the digital core
• ☐ RFIC analog sides face the RX edge

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• ☐ All major parts remain inside assigned regions
• ☐ No RX lane parts enter the center spine
• ☐ Digital escape remains reserved before RF routing begins

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• ☐ RX1 is fully inside its box
• ☐ RX2 is fully inside its box
• ☐ RX3 is fully inside its box
• ☐ RX4 is fully inside its box
• ☐ Upper pair uses the same template
• ☐ Lower pair uses the same template
• ☐ Outer lanes are equivalent
• ☐ Inner lanes are equivalent

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• ☐ Same part order in all 4 lanes
• ☐ Same component orientation in all 4 lanes
• ☐ Same X positions within <= 0.10 mm
• ☐ Same pad-to-pad spacing within <= 0.10 mm
• ☐ Same centerline offset discipline across all 4 lanes

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• ☐ Upper and lower halves were built from the same routing idea
• ☐ No one-off lane rescue routing exists
• ☐ No lane has unique detours, stubs, or extra transitions

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• ☐ All four lanes use the same layer stack strategy
• ☐ All four lanes use the same via count
• ☐ All four lanes use the same bend count
• ☐ All four lanes preserve return-path consistency
• ☐ If one lane changes topology, all peer lanes are updated to match

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• ☐ Both RFIC regions use the same local decoupling philosophy
• ☐ Both RFIC regions use the same clock/reference placement logic
• ☐ Both RFIC regions use the same ground stitching pattern
• ☐ Neither RFIC region steals area from the other’s routing template

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• Preferred baseline: 4 layers
• Do not drop below 4 layers if you want a clean solid reference plane under the RX lanes and controlled digital escape near the M.2 interface.

• Prefer routing all four RX lanes on L1, referenced to solid L2 ground.
• Keep L2 unbroken under the entire RX region and under both AD9363 support regions.
• Use L3 primarily for power distribution, filtered rail spreading, and lower-priority signals.
• Use L4 for secondary routing and support nets, not as the only solution for one difficult RX lane.
• If any RX lane must transition layers, the matching peer lanes should use the same transition count and same topology class.

• ☐ Final layer count selected
• ☐ L2 assigned as the primary uninterrupted ground reference
• ☐ RX lanes kept on the same primary routing layer
• ☐ L3 usage limited so it does not compromise return paths
• ☐ Any layer transitions mirrored across peer lanes

• Keep the copper-weight assumption identical for all impedance calculations.
• Re-solve all controlled widths if the board house changes copper thickness.
• Avoid changing from 0.5 oz to 1 oz on an inner layer without re-checking both impedance and current-density assumptions.

• Keep L1-L2 thin enough to support practical 50 ohm top-layer RF routing without excessively wide traces.
• Keep L2-L3 thick enough to preserve strong plane separation and power-distribution flexibility.
• Keep L3-L4 similar to L1-L2 if controlled routing or symmetry checks may also involve the bottom layer.
• Replace all planning values with exact fabricator stackup numbers before release.

• Solve trace widths from the actual board-house stackup, not from assumptions alone.
• Keep all four RX lanes on the same layer, same width, same copper thickness, and same reference-plane geometry.
• Do not allow one lane to gain a unique neckdown, anti-pad environment, or split crossing.
• Keep differential pair width and spacing constant through corresponding regions.
• Minimize vias on controlled-impedance nets.
• If one repeated lane requires a via, matching peer lanes should use an equivalent via topology when practical.
• Re-check impedance whenever copper weight, dielectric thickness, soldermask assumption, or trace geometry changes.

• ☐ Layer count documented
• ☐ Copper weights documented
• ☐ Dielectric targets documented
• ☐ 50 ohm targets assigned to RX lanes
• ☐ 100 ohm differential targets assigned where required
• ☐ Final solved widths and gaps recorded
• ☐ Controlled-net via policy recorded

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• ☐ Digital corridors were reserved before lane routing
• ☐ Center spine is not used as a convenience path
• ☐ Upper and lower RX pairs do not borrow each other’s route area

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• ☐ PASS - routing symmetry intent preserved
• ☐ REWORK - at least one lane or support region violates the template
• ☐ HOLD - placement must be corrected before routing continues

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• Date:
• Reviewer:
• Current revision:
• Main issues found:
• Required rework:
• Recheck complete:
• Fabricator stackup selected:
• Final 50 ohm width:
• Final 100 ohm differential width / gap:
• Controlled-net via policy:
• Final copper weights:
• Final dielectric values: