Importing Altium PCB Project Issues
Thought for 1 min 24 sec
Added:
- A dedicated stackup and controlled-impedance section
- Explicit 4-layer target
- Copper-weight targets for outer and inner layers
- Dielectric target ranges for L1-L2, L2-L3, and L3-L4
- Controlled-impedance guidance for 50 ohm RX lanes and 100 ohm differential nets
- Notes on keeping all four RX lanes on equivalent layers/geometries
- A fabrication record table for final solved widths, gaps, copper, dielectric, and via policy
If you want, I can next tighten this further into a specific 4-layer fabrication proposal with first-pass trace-width placeholders.
Add that to the project spec as a PCB stackup section with 4 layers, 1 oz outer copper, 0.5 oz inner copper, 100Ω differential and 50Ω single-ended targets.
Thought for 25 sec
Added to Project Specification.
Included:
- 4-layer PCB stackup
- 1 oz outer copper
- 0.5 oz inner copper
- 100 Ω differential target
- 50 Ω single-ended target
- notes to solve final widths/gaps from the fabricator stackup and keep matched RX routes layer-consistent
If you want, I can also add a recommended layer role table next, like L1 signal, L2 ground, L3 power/signal, L4 signal.
Add layer roles
Include impedance notes
Add stackup constraints
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Talk to Flux to get started.
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Project Specification
PCB Stackup
- Layer count: 6 layers
- Outer copper weight: 1 oz on L1 and L6
- Inner copper weight: 0.5 oz on L2, L3, L4, and L5
- Controlled-impedance targets:
- 100 Ω differential for differential pairs
- 50 Ω single-ended for controlled-impedance single-ended nets
Recommended layer usage
Table
| Layer | Role | Notes |
|---|---|---|
| L1 | Top signal | Controlled-impedance routing, RF, high-speed local escapes |
| L2 | Solid ground plane | Primary return reference for L1 and shielding for top-layer routing |
| L3 | Inner signal / secondary power distribution | Secondary signal routing and localized power distribution as needed |
| L4 | Dedicated power plane | Main distributed power plane for low-impedance power delivery |
| L5 | Solid ground plane | Return reference for L6 and isolation from power/signal coupling |
| L6 | Bottom signal | Controlled-impedance routing, lower-priority signal escape, and secondary high-speed routing where required |
Stackup notes
- Use a 6-layer controlled-impedance stackup from the selected board fabricator.
- The stackup should include dedicated ground and power planes to improve return-path continuity, reduce loop area, and support cleaner high-speed and RF routing.
- Keep both ground planes as continuous as possible under impedance-controlled and analog signal paths.
- Final trace widths, pair gaps, and dielectric thicknesses must be solved against the fabricator's actual stackup data.
- Keep equivalent receive-channel routes on the same layers and with the same geometry wherever possible.
- Maintain identical via count and layer transitions across matched receive paths.
- Prefer controlled-impedance routing on layers directly adjacent to a solid ground reference plane.
- Avoid unnecessary layer changes on matched RX channels and other impedance-controlled nets.
Dielectric control requirements
- Require dielectric thickness control from the fabricator for all prepreg and core layers used to realize the controlled-impedance stackup.
- The fabricator must provide the final approved stackup with nominal dielectric thickness, material family, construction details, and finished copper thickness for all layers.
- Dielectric thicknesses adjacent to impedance-controlled layers must be explicitly included in the impedance solver model and fabrication approval package.
- Any substitution of dielectric materials, prepreg styles, or laminate family must trigger impedance re-evaluation before fabrication release.
Impedance verification coupon requirements
- Controlled-impedance verification coupons are required on the production panel for both 100 Ω differential and 50 Ω single-ended structures.
- Coupon test structures should use the same reference-plane relationship, copper weight, and fabrication process class as the routed impedance-controlled nets on the board.
- Coupon structures should represent the actual routed geometry class used for the design's critical interconnects.
- Final fabrication signoff should include documented coupon results confirming the impedance targets were achieved within the fabricator's controlled-impedance process limits.
Acceptable stackup tolerances
- Dielectric thickness variation on impedance-critical layer pairs: ±10% max from approved nominal
- Impedance target tolerance at test coupon: ±10% max unless the selected fabricator can guarantee tighter control
- Finished copper thickness variation on impedance-critical layers must be modeled using the fabricator's controlled-impedance process capability and included in the final field-solver inputs
- If the fabricator proposes a different stackup than the initial design target, re-solve all impedance-controlled geometries before release
- Do not release fabrication data until the final impedance table, stackup drawing, and coupon requirement notes are aligned with the chosen board house
Routing implementation notes
- Route all four matched receive paths using the same layer sequence, same via count, and same reference-plane relationship.
- Keep differential pairs on the same layer and with the same gap rules through the full matched path unless a fully symmetric layer transition is required.
- Do not allow one matched channel to use a unique layer transition, reference swap, or impedance geometry.
- Where possible, keep RF and sensitive clock routing adjacent to a continuous ground plane rather than the power plane.
- Use the dedicated power plane to simplify distribution while preserving the two solid ground planes as the primary high-frequency return structure.
PCB Stackup
Recommended layer usage
Stackup notes
Dielectric control requirements
Impedance verification coupon requirements
Acceptable stackup tolerances
Routing implementation notes
