Schematic Design Issue Review
Thought for 3 mins 12 sec
Here is a focused, schematic-level review of your current design. I’m only calling out what is directly observable in the schematic and BOM.
Electrical and logical issues
- Power pin connectivity
- SPI wiring
- SWD wiring
- Reset net
- Button input
- Unused/legacy net portals
- Multiple Net Portal components (e.g., named for SPI, reset, crystal, button) are placed but not actually connected to the functional nets. The active nets carry generic names (Net 7/Net 6/Net 16/Net 15/Net 14/Net 10/etc.). This is confusing and risks accidental miswires later.
Component-level review
- Decoupling and bulk caps
- LED current limiting
- SWD series damping
- Battery input
- J1 POS connects to VBAT; NEG to GND. No reverse-polarity or input transient protection components are present on VBAT.
Power and signal integrity
- Power distribution
- Signal integrity
- Series resistors are only on SWD lines. SPI lines (Net 6/7/16/15) have no series terminations in the schematic; nothing inherently wrong is visible here at schematic level.
Schematic best practices and net labeling
- Generic net names on critical signals
- SPI and other key nets use generic names: Net 7 (MOSI), Net 6 (MISO), Net 16 (SCLK), Net 15 (ACC_CS), Net 8 (ACC_INT1), Net 2 (ACC_INT2), Net 10 (BUTTON), Net 3 (LED), Net 14 (RESET). Rename these nets to their functional names so they are self-documenting and recognized clearly by ERC.
- Unused legacy portals
- Remove or connect the stray Net Portal components intended for SPI/RESET/XTAL/BUTTON so the net names match the intended signal names. Keeping unconnected portals increases the chance of mistakes.
- Power net metadata
- Add a voltage property to VBAT and mark it as a Power net type. Clear power net naming and properties improve ERC/DRC behavior and readability.
Actionable corrections and optimizations
- Reset net
- Button input
- Observation: No external pull-up/down on U2 P0.17 (button net). Action: If you are not relying on the MCU’s internal pull, add the appropriate pull resistor.
- Net labeling cleanup
- Rename the following nets:
- Net 7 -> MOSI
- Net 6 -> MISO
- Net 16 -> SCLK
- Net 15 -> ACC_CS
- Net 8 -> ACC_INT1
- Net 2 -> ACC_INT2
- Net 10 -> BUTTON
- Net 3 -> LED
- Net 14 -> RESET
- Delete or properly connect the currently unconnected Net Portal components for these signals.
- Rename the following nets:
- Power net properties
- Set VBAT as a Power net and add its voltage value in net properties.
- Battery input robustness (optional improvement)
What I verified via project data
- ERC summary: No schematic-level ERC errors reported (Missing Power, Pin-to-Pin conflicts, Single pin nets, Undriven nets all clear).
- Crystal network is correctly cross-connected with its two load capacitors to GND.
- LED has a series resistor; SWD lines have series resistors; decoupling and bulk capacitors exist on VBAT.
- Several disconnected Net Portals exist while the live nets remain generically named.
If you want, I can:
- Rename the nets listed above and remove the stray Net Portal instances.
- Add pull resistors on RESET and the BUTTON input if you confirm they’re needed.
