CameraPen Project Specification

I applied the targeted cleanup without touching the main routed trace set: disabled/shrunk U6 dummy mount pads, disabled DRC-listed via/fill/stitch artifacts, and added RF launch width/0.5 mm keepout rules around the LNA/antenna feed.
DRC is still not clean: the checker continues to report the same 42 overlap items, which indicates these are generated footprint/route artifacts that are not being removed by normal layout-rule overrides; the RF route also cannot be manually completed because the matching-network pad net metadata is inconsistent (U6:LNA_IN on RF_ESP32_FEED, ANT1:1 on RF_ANT_FEED, and C15 pad appears empty to the router).
Next best fix is schematic/layout net cleanup for the RF pi-match chain, then regenerate the U6 footprint without the dummy mount pads instead of trying to suppress them in layout.
I executed the RF net metadata fix: merged the ESP32 RF feed and antenna-side feed into a single RF_ANT_FEED net, then successfully routed U6:LNA_IN → ANT1:1.
DRC is still not clean: after refresh it reports 7 airwires and 45 overlap errors; the remaining overlaps are still generated via/through-hole/U6 dummy-pad artifacts that normal layout overrides are not clearing. Also note the RF route was completed but is not final RF-quality yet because the router used a long multi-layer path with vias; the next real fix is to regenerate/replace the U6 footprint and RF matching layout, not keep suppressing generated artifacts.
Rebuild RF and U6
Regenerate U6 footprint
Rebuild RF layout
Fix J3 artifacts
Update review notes
U6
U3
C7
Capacitance
1uF
J1 EH - U2 V_{SS}
C12 P2 - C13 P2
C12 P2 - C13 P2
U1 GND - R1 P2
C12
Capacitance
100nF
U1 GND - R1 P2
C11
Capacitance
100nF
C12 P2 - C13 P2
J1 EH - U2 V_{SS}
J1 EH - U2 V_{SS}
C15
Capacitance
DNI F
J1 EH - U2 V_{SS}
C1
Capacitance
4.7uF
C4
Capacitance
4.7uF
GND
GND
TP_CHG_N P1 - TP_SEC_N P1
U4 VSS - U5 GND
J1 EH - U2 V_{SS}
U6 GND - C9 P2
C6
Capacitance
1uF
C10
Capacitance
100nF
U4 VSS - U5 GND
GND
U6 GND - C9 P2
U6 GND - C9 P2
U4 VSS - U5 GND
U4 VSS - U5 GND
C12 P2 - C13 P2
U4 VSS - U5 GND
C12 P2 - C13 P2
C16
Capacitance
DNI F
C2
Capacitance
4.7uF
C13
Capacitance
10pF
C9
Capacitance
10µF
C12 P2 - C13 P2
U1 GND - R1 P2
U4 VSS - U5 GND
U4 VSS - U5 GND
C12 P2 - C13 P2
U4 VSS - U5 GND
C3
Capacitance
1uF
J1 EH - U2 V_{SS}
U6 GND - C9 P2
C14
Capacitance
10pF
U4 VSS - U5 GND
C8
Capacitance
1uF
C5
Capacitance
1uF
U4 VSS - U5 GND
TP_CHG_N P1 - TP_SEC_N P1
C12 P2 - C13 P2
J1 EH - U2 V_{SS}
U2 V_{BAT} - J2 1
CAM_RESET
U6 VDD_SPI - C9 P1
CAM_D2
U6 GPIO8 - R8 P2
U6 GPIO9 - R9 P2
R10 P2 - C12 P1
U6 VDD3P3_RTC - U6 VDD3P3_CPU
U6 VDD_SPI - C9 P1
U5 VOUT - C8 P1
U6 U0RXD - TP_RXD P1
U3 EN - C2 P1
U6 VDD_SPI - C9 P1
U3 EN - C2 P1
U6 GPIO9 - R9 P2
CAM_D0
CAM_D5
J1 VBUS - U2 V_{DD}
U2 V_{BAT} - J2 1
U5 VOUT - C8 P1
CAM_D1
R5 P2 - R6 P1
R4 P2 - SW1 1
U6 LNA_IN - L1 P1
CAM_D3
CAM_MCLK
CAM_D6
U2 V_{BAT} - J2 1
U6 VDD3P3_RTC - U6 VDD3P3_CPU
U2 PROG - R1 P1
U6 XTAL_N - Y1 P3
CAM_D6
CAM_VSYNC
U6 LNA_IN - L1 P1
R4 P2 - SW1 1
U6 VDD3P3 - U6 VDD3P3
U3 EN - C2 P1
CAM_RESET
J1 VBUS - U2 V_{DD}
U4 VOUT - C6 P1
CAM_D7
U6 VDD3P3 - U6 VDD3P3
U4 VOUT - C6 P1
U2 V_{BAT} - J2 1
U5 VOUT - C8 P1
U6 VDD_SPI - C9 P1
U6 LNA_IN - L1 P1
U6 U0TXD - TP_TXD P1
CAM_PCLK
U6 U0TXD - TP_TXD P1
U6 VDD_SPI - C9 P1
CAM_PWDN
R5 P2 - R6 P1
U6 VDD3P3_RTC - U6 VDD3P3_CPU
U2 V_{BAT} - J2 1
U2 V_{BAT} - J2 1
R5 P2 - R6 P1
J1 VBUS - U2 V_{DD}
R10 P2 - C12 P1
U6 VDD3P3_RTC - U6 VDD3P3_CPU
R4 P2 - SW1 1
R4 P2 - SW1 1
R10 P2 - C12 P1
U6 U0RXD - TP_RXD P1
U6 XTAL_N - Y1 P3
U6 VDD_SPI - C9 P1
CAM_D1
U6 LNA_IN - L1 P1
CAM_D5
U6 XTAL_P - Y1 P1
U4 VOUT - C6 P1
CAM_D7
U2 PROG - R1 P1
U6 LNA_IN - L1 P1
CAM_D4
U6 GPIO8 - R8 P2
U4 CE - C5 P1
U6 VDD_SPI - C9 P1
CAM_PCLK
U4 CE - C5 P1
U5 VOUT - C8 P1
CAM_D0
CAM_PWDN
U6 VDD_SPI - C9 P1
U6 GPIO8 - R8 P2
CAM_MCLK
CAM_HREF
U6 GPIO9 - R9 P2
CAM_D2
U6 XTAL_N - Y1 P3
U6 VDD_SPI - C9 P1
U6 LNA_IN - L1 P1
CAM_D4
R10 P2 - C12 P1
U6 XTAL_P - Y1 P1
U4 CE - C5 P1
CAM_VSYNC
U6 VDD_SPI - C9 P1
CAM_HREF
CAM_D3
U6 VDD_SPI - C9 P1
U6 XTAL_P - Y1 P1
J2
TP_TXD
R10
Resistance
10kΩ
R8
Resistance
4.7kΩ
TP_BOOT
R6
Resistance
100kΩ
TP_CHG_N
TP_SEC_P
R5
Resistance
25.5kΩ
TP_CHG_P
U5
TP_3V3
ANT1
R9
Resistance
4.7kΩ
SW1
TP_EN
R4
Resistance
10kΩ
U4
R1
Resistance
10kΩ
L1
Inductance
0nH/DNI tune H
TP_GND
U2
J3
TP_RXD
TP_SEC_N
Y1

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CameraPen Project Specification
Goal
Design a miniature camera pen electronics system that fits inside a two-section pen body using a bare OV3660 camera module, three custom miniature PCBs, and a narrow custom/rigid-flex implementation.
Mechanical Envelope / Section Plan
The complete pen length after the two sections are screwed together is 138 mm.
Section ① — Lower / Writing-Grip Section
  • Mechanical role: battery and charging/power-entry subsystem.
  • Usable allocation: 55 mm battery + 12 mm charging PCB = 67 mm.
  • Internal diameter at the thread side: about 8 mm.
  • Contains:
    • Slim cylindrical LiPo battery.
    • Charging PCB / power-management PCB.
    • Inter-section power contacts to feed the upper electronics section.
Section ② — Upper / Cap Section
  • Nominal length: 83 mm.
  • Effective usable electronics length after subtracting the 12 mm overlap/thread region: about 71 mm.
  • Internal diameter/channel: about 9 mm.
  • Contains, in order:
    1. Camera PCB / FFC connector region.
    2. OV3660 camera module with lens.
    3. Main PCB with ESP32-S3R8-class controller and memory/support circuitry.
    4. Button at the far end of the main PCB near the cap/clip end.
System Sorting
Mechanical/electrical chain:
Battery → Charging PCB → Camera PCB → OV3660 → Main PCB ESP32-S3R8 → Button
Power originates in Section ①, passes through the Charging PCB, crosses the mechanical joint through dedicated contacts, then feeds the camera and main electronics in Section ②. Camera image data routes from the OV3660/camera PCB to the main processor PCB.
PCB Architecture
The final product should use three separate PCBs:
  1. Charging PCB
    • Located in Section ① after the battery.
    • Handles battery charging and power entry.
    • Final design should not use USB-C on the pen body because it is too large for the mechanical envelope.
    • Charging should use concentric copper contact pads on one side and gold-plated pogo pins on the mating charger/dock side.
  2. Camera PCB
    • Located at the camera end of Section ②.
    • Carries the OV3660 FFC/FPC connector and local camera power/filtering as needed.
    • Connects to Main PCB through a very short flex/interconnect.
  3. Main PCB
    • Located in Section ② after the camera area.
    • Carries ESP32-S3R8-class MCU/SoC, memory, regulators/support circuits, programming/debug pads, and button interface.
Electrical Architecture
  • Single-cell LiPo battery power source.
  • Final charging input: external charger/dock using pogo pins contacting concentric copper pads.
  • USB-C may remain only as a prototype/debug charging option if kept off the final pen assembly.
  • LiPo charger: MCP73831-class single-cell charger or equivalent small charger IC.
  • Main logic rail: 3.3 V.
  • Final controller target: ESP32-S3R8 or equivalent custom-board controller capable of OV3660 DVP capture.
  • OV3660 camera connected through J3, Molex 505110-2491 24-pin 0.5 mm bottom-contact FFC/FPC connector, or an orientation-compatible equivalent.
  • Camera rails:
    • CAM_2V8 for AVDD/DOVDD.
    • CAM_1V5 for DVDD.
  • Camera DVP/SCCB signals: CAM_D0CAM_D7, CAM_PCLK, CAM_HREF, CAM_VSYNC, CAM_MCLK, CAM_SIOC, CAM_SIOD, CAM_RESET, CAM_PWDN.
J3 / OV3660 Pinout Basis
The schematic maps J3 by pin number to the IADIY-style OV3660 DVP 24-pin pinout:

Table


J3 PinFunction
1NC
2AGND / GND
3SIOD
4AVDD 2.8 V
5SIOC
6RESET
7VSYNC
8PWDN
9HREF
10DVDD 1.5 V
11DOVDD 2.8 V
12D7
13MCLK
14D6
15DGND / GND
16D5
17PCLK
18D4
19D0
20D3
21D1
22D2
23NC
24NC
Key Constraints / Risks
  • The internal diameters are only about 8 mm and 9 mm, so all final PCBs must be narrow custom boards or rigid/flex boards.
  • The previous ESP32-CAM module reference is not mechanically valid for the final pen.
  • The OV3660 FPC tail is about 12–12.5 mm wide, larger than the stated 9 mm barrel ID if routed straight.
  • The Section ①/② joint and thread overlap are the critical routing zone for power contacts and any flex/fold geometry.
  • J3 is a bottom-contact connector. The actual camera FPC contact side, pin-1 side, cable exit direction, and footprint pin numbering must be verified before layout release and before applying camera power.
  • A reversed FPC orientation could place 2.8 V or 1.5 V on data/GND pins and damage the camera.
  • Concentric charging contacts need mechanical isolation, polarity protection, short-circuit tolerance, and a charger dock design that prevents reverse contact.
Acceptance Criteria
  • Schematic includes battery, charging/power regulation, inter-section power contacts, button input, controller/camera interface, and required passives.
  • Design files clearly separate Charging PCB, Camera PCB, and Main PCB responsibilities.
  • Final layout phase must verify each board width below the usable inner diameter after wall/clearance allowance.
  • Inter-section power contacts must be keyed/polarity-safe and testable.
  • J3 assembly drawing must show pin 1, insertion direction, bottom-contact requirement, and expected FPC contact side.
  • First power-up must verify camera connector rails with the camera unplugged before inserting the OV3660 module.
Change Notes
  • Updated from USB-C final charging to pogo/concentric-pad charging because USB-C is too large for the pen body.
  • Confirmed final mechanical allocation: Section ① = 67 mm; Section ② usable electronics length ≈ 71 mm.
  • Confirmed three-PCB architecture: Charging PCB, Camera PCB, Main PCB.
  • Goal

  • Mechanical Envelope / Section Plan

  • Section ① — Lower / Writing-Grip Section

  • Section ② — Upper / Cap Section

  • System Sorting

  • PCB Architecture

  • Electrical Architecture

  • J3 / OV3660 Pinout Basis

  • Key Constraints / Risks

  • Acceptance Criteria

  • Change Notes

Assets

Assets are files uploaded to this project which can be used in various ways.

CameraPen thumbnail
Welcome to your new project. Imagine what you can build here.

Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$0.37–$0.59

Digi-Key

$2.43

HQonline

$3.54–$3.58

LCSC

$4.31

Mouser

$4.59

TME

$1.58

Verical

$0.69–$0.79

Controls