CameraPen Project Specification

I applied the targeted cleanup without touching the main routed trace set: disabled/shrunk U6 dummy mount pads, disabled DRC-listed via/fill/stitch artifacts, and added RF launch width/0.5 mm keepout rules around the LNA/antenna feed.
DRC is still not clean: the checker continues to report the same 42 overlap items, which indicates these are generated footprint/route artifacts that are not being removed by normal layout-rule overrides; the RF route also cannot be manually completed because the matching-network pad net metadata is inconsistent (U6:LNA_IN on RF_ESP32_FEED, ANT1:1 on RF_ANT_FEED, and C15 pad appears empty to the router).
Next best fix is schematic/layout net cleanup for the RF pi-match chain, then regenerate the U6 footprint without the dummy mount pads instead of trying to suppress them in layout.
I executed the RF net metadata fix: merged the ESP32 RF feed and antenna-side feed into a single RF_ANT_FEED net, then successfully routed U6:LNA_IN → ANT1:1.
DRC is still not clean: after refresh it reports 7 airwires and 45 overlap errors; the remaining overlaps are still generated via/through-hole/U6 dummy-pad artifacts that normal layout overrides are not clearing. Also note the RF route was completed but is not final RF-quality yet because the router used a long multi-layer path with vias; the next real fix is to regenerate/replace the U6 footprint and RF matching layout, not keep suppressing generated artifacts.
Rebuild RF and U6
Regenerate U6 footprint
Rebuild RF layout
Fix J3 artifacts
Update review notes
U6
U3
C7
Capacitance
1uF
J1 EH - U2 V_{SS}
C12 P2 - C13 P2
C12 P2 - C13 P2
U1 GND - R1 P2
C12
Capacitance
100nF
U1 GND - R1 P2
C11
Capacitance
100nF
C12 P2 - C13 P2
J1 EH - U2 V_{SS}
J1 EH - U2 V_{SS}
C15
Capacitance
DNI F
J1 EH - U2 V_{SS}
C1
Capacitance
4.7uF
C4
Capacitance
4.7uF
GND
GND
TP_CHG_N P1 - TP_SEC_N P1
U4 VSS - U5 GND
J1 EH - U2 V_{SS}
U6 GND - C9 P2
C6
Capacitance
1uF
C10
Capacitance
100nF
U4 VSS - U5 GND
GND
U6 GND - C9 P2
U6 GND - C9 P2
U4 VSS - U5 GND
U4 VSS - U5 GND
C12 P2 - C13 P2
U4 VSS - U5 GND
C12 P2 - C13 P2
C16
Capacitance
DNI F
C2
Capacitance
4.7uF
C13
Capacitance
10pF
C9
Capacitance
10µF
C12 P2 - C13 P2
U1 GND - R1 P2
U4 VSS - U5 GND
U4 VSS - U5 GND
C12 P2 - C13 P2
U4 VSS - U5 GND
C3
Capacitance
1uF
J1 EH - U2 V_{SS}
U6 GND - C9 P2
C14
Capacitance
10pF
U4 VSS - U5 GND
C8
Capacitance
1uF
C5
Capacitance
1uF
U4 VSS - U5 GND
TP_CHG_N P1 - TP_SEC_N P1
C12 P2 - C13 P2
J1 EH - U2 V_{SS}
U2 V_{BAT} - J2 1
CAM_RESET
U6 VDD_SPI - C9 P1
CAM_D2
U6 GPIO8 - R8 P2
U6 GPIO9 - R9 P2
R10 P2 - C12 P1
U6 VDD3P3_RTC - U6 VDD3P3_CPU
U6 VDD_SPI - C9 P1
U5 VOUT - C8 P1
U6 U0RXD - TP_RXD P1
U3 EN - C2 P1
U6 VDD_SPI - C9 P1
U3 EN - C2 P1
U6 GPIO9 - R9 P2
CAM_D0
CAM_D5
J1 VBUS - U2 V_{DD}
U2 V_{BAT} - J2 1
U5 VOUT - C8 P1
CAM_D1
R5 P2 - R6 P1
R4 P2 - SW1 1
U6 LNA_IN - L1 P1
CAM_D3
CAM_MCLK
CAM_D6
U2 V_{BAT} - J2 1
U6 VDD3P3_RTC - U6 VDD3P3_CPU
U2 PROG - R1 P1
U6 XTAL_N - Y1 P3
CAM_D6
CAM_VSYNC
U6 LNA_IN - L1 P1
R4 P2 - SW1 1
U6 VDD3P3 - U6 VDD3P3
U3 EN - C2 P1
CAM_RESET
J1 VBUS - U2 V_{DD}
U4 VOUT - C6 P1
CAM_D7
U6 VDD3P3 - U6 VDD3P3
U4 VOUT - C6 P1
U2 V_{BAT} - J2 1
U5 VOUT - C8 P1
U6 VDD_SPI - C9 P1
U6 LNA_IN - L1 P1
U6 U0TXD - TP_TXD P1
CAM_PCLK
U6 U0TXD - TP_TXD P1
U6 VDD_SPI - C9 P1
CAM_PWDN
R5 P2 - R6 P1
U6 VDD3P3_RTC - U6 VDD3P3_CPU
U2 V_{BAT} - J2 1
U2 V_{BAT} - J2 1
R5 P2 - R6 P1
J1 VBUS - U2 V_{DD}
R10 P2 - C12 P1
U6 VDD3P3_RTC - U6 VDD3P3_CPU
R4 P2 - SW1 1
R4 P2 - SW1 1
R10 P2 - C12 P1
U6 U0RXD - TP_RXD P1
U6 XTAL_N - Y1 P3
U6 VDD_SPI - C9 P1
CAM_D1
U6 LNA_IN - L1 P1
CAM_D5
U6 XTAL_P - Y1 P1
U4 VOUT - C6 P1
CAM_D7
U2 PROG - R1 P1
U6 LNA_IN - L1 P1
CAM_D4
U6 GPIO8 - R8 P2
U4 CE - C5 P1
U6 VDD_SPI - C9 P1
CAM_PCLK
U4 CE - C5 P1
U5 VOUT - C8 P1
CAM_D0
CAM_PWDN
U6 VDD_SPI - C9 P1
U6 GPIO8 - R8 P2
CAM_MCLK
CAM_HREF
U6 GPIO9 - R9 P2
CAM_D2
U6 XTAL_N - Y1 P3
U6 VDD_SPI - C9 P1
U6 LNA_IN - L1 P1
CAM_D4
R10 P2 - C12 P1
U6 XTAL_P - Y1 P1
U4 CE - C5 P1
CAM_VSYNC
U6 VDD_SPI - C9 P1
CAM_HREF
CAM_D3
U6 VDD_SPI - C9 P1
U6 XTAL_P - Y1 P1
J2
TP_TXD
R10
Resistance
10kΩ
R8
Resistance
4.7kΩ
TP_BOOT
R6
Resistance
100kΩ
TP_CHG_N
TP_SEC_P
R5
Resistance
25.5kΩ
TP_CHG_P
U5
TP_3V3
ANT1
R9
Resistance
4.7kΩ
SW1
TP_EN
R4
Resistance
10kΩ
U4
R1
Resistance
10kΩ
L1
Inductance
0nH/DNI tune H
TP_GND
U2
J3
TP_RXD
TP_SEC_N
Y1

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CameraPen Board Bring-Up Plan
Before Power-On
  • Inspect USB-C connector, battery connector polarity, charger IC orientation, LDO orientation, J3 camera FFC orientation, and all passives.
  • Confirm selected LiPo cell capacity and safe charge current; current schematic uses R1 = 10 kΩ as an initial low-current charger setting.
  • Confirm whether the final controller is the ESP32-CAM prototype reference or a custom narrow PCB.
  • Do not insert the OV3660 camera before validating J3 power pins and orientation.
J3 / OV3660 Orientation Checks Before Camera Insertion
  1. Confirm J3 is Molex 505110-2491 bottom-contact connector.
  2. Confirm the camera FPC tail has exposed contacts facing the correct side for bottom-contact insertion.
  3. Confirm physical pin 1 on the camera FPC using the exact module drawing or continuity/breakout test.
  4. Confirm the inserted orientation maps:
    • Camera pin 2 and pin 15 → board GND.
    • Camera pin 4 and pin 11 → board CAM_2V8.
    • Camera pin 10 → board CAM_1V5.
  5. If pin order appears reversed, stop; do not power the camera.
Power Checks Without Camera Installed
  1. With no battery installed, plug USB-C into a current-limited supply and verify USB_5V is about 5 V.
  2. Install a protected 1-cell LiPo and verify VBAT is approximately 3.0–4.2 V.
  3. Verify 3V3 output from the main LDO is approximately 3.3 V.
  4. Verify J3 pin 4 and pin 11 are approximately 2.8 V on CAM_2V8.
  5. Verify J3 pin 10 is approximately 1.5 V on CAM_1V5.
  6. Verify J3 pin 2 and pin 15 are GND.
  7. Check charger and LDO temperatures during the first charge/power test.
First Camera Power-Up
  • Use a current-limited bench supply for the first camera insertion/power-up.
  • Insert the OV3660 FPC only after the no-camera voltage checks pass.
  • Start with firmware holding CAM_PWDN/CAM_RESET in a safe state if available.
  • Monitor input current and camera rail voltages during enable.
Functional Checks
  • Press SW1 and confirm the BUTTON net pulls low.
  • Program/test prototype controller firmware.
  • Initialize OV3660 over SCCB/I²C using CAM_SIOC and CAM_SIOD.
  • Verify MCLK output, VSYNC/HREF/PCLK activity, and D0–D7 data activity.
  • Capture a still image or test frame.
  • Measure sleep current and active capture current to estimate battery life.
Mechanical Checks
  • Confirm every selected part fits inside the 8–9 mm internal diameter after wall clearance.
  • Confirm whether the 12–12.5 mm camera FPC tail can physically fit or fold within the rear barrel.
  • For production, plan a long narrow PCB or rigid-flex, with button in Section ①, battery in Section ①, PCB in Section ②, and camera at the rear end.
  • Before Power-On

  • J3 / OV3660 Orientation Checks Before Camera Insertion

  • Power Checks Without Camera Installed

  • First Camera Power-Up

  • Functional Checks

  • Mechanical Checks

Assets

Assets are files uploaded to this project which can be used in various ways.

CameraPen thumbnail
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Properties

Properties describe core aspects of the project.

Pricing & Availability

Distributor

Qty 1

Arrow

$0.37–$0.59

Digi-Key

$2.43

HQonline

$3.54–$3.58

LCSC

$4.31

Mouser

$4.59

TME

$1.58

Verical

$0.69–$0.79

Controls