High-Speed Energy Transfer System Design

0:00

Work done

Inspected the existing schematic/BOM/layout and found a 246-component schematic, 4-layer 200 mm × 120 mm PCB, and unresolved airwire errors.
Added HV hardening circuitry: 400 V bus TVS clamp, precharge resistor, two-resistor bleeders for both HV capacitor banks, gate-source zener clamps, gate pulldowns, and RC snubbers for Q1–Q8.
Added a DNI/SPICE simulation load placeholder for 400 V / 8 kW equivalent loading.
Corrected key unsafe metadata: ES1J bootstrap diode reverse-voltage/type notes and C_A/C_B HV capacitor voltage/package review notes.
Re-applied a 4-layer stackup and 200 mm × 120 mm board with 4 mm keepout/inset policy.
Re-placed the PCB so the added protection parts are grouped around HV input, capacitor banks, and MOSFET power stages with no placement overlap or out-of-bounds issues reported by the placement pass.

Success criteria review

✅ Added major HV protection blocks and documented ratings/roles on the new components.
✅ Updated several flawed/suspect component properties and flagged remaining mechanical/thermal review items.
✅ Added simulation load placeholder for transient readiness.
✅ Updated 4-layer PCB sizing/stackup/keepout rules and component placement.
❌ Could not complete final routing, ERC/DRC iteration, airwire cleanup, or manufacturing-export validation because execution credits are exhausted.

Next steps

Continue with direct schematic verification of the repaired gate/source/snubber nets, then run the remaining ERC/DRC remediation loop: clear airwires, route the PCB, check for clearance/overlap/copper issues, and re-run review until exportable. After that, proceed to final PCB routing/layout validation and manufacturing export preparation.

Started implementing a plan

## High-level goal

Update the existing Flux project for a **400 V / 8 kW switched-capacitor energy transfer** power stage so it is protection-hardened, simulation-ready, and PCB-constrained (notably **4 mm clearance/keepout** between logic-ground copper and HV nets), following the provided line-by-line netlist and ensuring the design is routable/manufacturable.

## What’s been done so far (in this session)

- **Inspected project state**: schematic has ~246 components / 43 nets; PCB is **200 mm × 120 mm**, **4-layer**, with 39 original footprints placed.

- **Identified major blocking issue**: layout review shows **Airwires (unrouted connections) errors**; board is not yet electrically realized on PCB.

- **Added protection + simulation placeholder circuitry to schematic**:

- **HV bus TVS clamp**: added **D_TVS_HV = SMAJ440A-TP** and connected **VBUS_400V ↔ GND_PWR**.

- **Gate protection for all 8 SiC MOSFETs**: added **R_GS1–R_GS8 (10 kΩ pulldowns)** and **DZ_G1–DZ_G8 (BZT52C18 zeners)**, then repaired connections so each set correctly ties to its MOSFET’s **G/S** and existing gate resistors.

- **RC snubbers per MOSFET**: added **R_SNUB1–R_SNUB8 (10 Ω)** in series with **C_SNUB1–C_SNUB8 (1 nF)** and connected each series RC across each MOSFET **D–S**.

- **Capacitor bleeders**: added **R_BLEED_A1/A2** across **C_A** and **R_BLEED_B1/B2** across **C_B** (two series parts each; midpoint nets created by connection side effect).

- **Precharge/inrush element**: added and connected **R_PRECHG (100 Ω placeholder)** from **VBUS_400V → CAP_A_POS**.

- **Simulation load placeholder**: added **R_LOAD_SIM (20 Ω)** and connected **LOAD_POS_SENSOR_OUT → LOAD_NEG** (marked as exclude-from-BOM/PCB).

- **Corrected misleading part metadata**:

- Updated **D1–D4 (ES1J)** properties to reflect **600 V** fast-recovery intent (library mismatch noted).

- Marked **C_A/C_B** as **450 V electrolytic** requiring a **radial/snap-in HV footprint** (footprint mismatch still suspected).

- **PCB constraints and placement updates**:

- Re-applied **Standard 4-layer stackup**.

- Set project-level layout rules including **keepOut = 4 mm** and **boardInsetMargin = 4 mm**.

- Ran AI placement to place **newly added protection parts** into functional clusters: TVS+precharge near J1, bleeders near C_A/C_B, and snubber/clamp networks near Q1–Q8; no overlaps/out-of-bounds.

## Implementation plan (remaining work only)

1. **Extract and verify the intended topology/sequence from the user-provided PDF and/or the strict netlist** and reconcile it against the current schematic nets (especially VBUS_400V, CAP_A/B rails, LOAD rails, and gate-driver channel mapping). Make any required schematic connection corrections to match the canonical netlist.

2. **Resolve critical footprint/part mismatches**:

- Replace **C_A/C_B** with correct **high-voltage electrolytic** parts/footprints available in Flux library (or select a suitable library part) so the PCB matches physical reality.

- Replace/confirm **D1–D4** with an actually-correct **600 V fast diode** library part (not just property edits) and ensure footprint matches assembly intent.

3. **Complete schematic power-integrity and gate-driver support network verification** for UCC21520 channels (U3–U6): confirm VCCI/VDDA/VSS decoupling, bootstrap diode/cap orientation, and that each OUTA/OUTB routes through the correct series gate resistor to the intended MOSFET gate.

4. **Run schematic ERC and fix remaining electrical issues** (unconnected power pins, single-pin nets, inconsistent grounds), prioritizing items that will prevent successful PCB routing.

5. **Clean the PCB of any stale routing artifacts** (run dangling-trace check if present; delete dangling segments if found), then **auto-route** all nets with priority rules for HV/current paths.

6. **Create/verify HV vs logic separation on the PCB**:

- Enforce **≥4 mm clearance** between **logic ground copper** and **VBUS_400V / CAP rails / LOAD rails**.

- Add keepout regions/slots if needed to maintain creepage.

7. **Place remaining unplaced parts (if any) and refine placement** for current loops and measurement accuracy (ACS730 routing, Kelvin sense if applicable), then re-run auto-route for improved current path quality.

8. **Run DRC until clean** (no airwires, no clearance violations, no missing footprints) and adjust layout rules (trace widths, via sizes) to meet 8 kW current handling assumptions.

9. **Make simulation explicitly runnable in Flux**:

- Add/verify the required transient directive **`.tran 0 10m 0 10n`**.

- Add appropriate sources/switch models placeholders if missing, and label/probe nodes for key waveforms (VBUS, CAP_A/B, LOAD, gate voltages).

10. **Manufacturability review**: check BOM availability for selected HV passives, verify footprints, silkscreen polarity, courtyard/assembly clearances, connector placement, and produce final notes for fabrication/assembly constraints.

Execution stopped by user.

10:52

Thought for 6 sec

Read knowledge.

Read schematic.

Thought for 2 sec

Read schematic.

Thought for 1 sec

Thought for 3 sec

Connected ^VBUS_400V, ^GND_PWR, ^CAP_A_POS, and 6 more, disconnected 78 pins

8:43

Connected J1:1, D_TVS_HV:C, R_PRECHG:P1, Q1:D, Q5:D, R_SNUB1:P1, R_SNUB5:P1 to ^VBUS_400V

Connected J1:2, D_TVS_HV:A, U3:VSSB, U5:VSSB, Q2:S, Q6:S, R_GS2:P2, DZ_G2:A, R_GS6:P2, DZ_G6:A, C_SNUB2:P2, C_SNUB6:P2 to ^GND_PWR

Connected Q1:S, Q3:D, C_A:P1, U3:VSSA, C_BOOT1:P2, R_BLEED_A1:P1, R_PRECHG:P2, R_GS1:P2, DZ_G1:A, C_SNUB1:P2, R_SNUB3:P1 to ^CAP_A_POS

Connected Q2:D, Q4:S, C_A:P2, U4:VSSB, R_BLEED_A2:P2, R_GS4:P2, DZ_G4:A, C_SNUB4:P2, R_SNUB2:P1 to ^CAP_A_NEG

Connected Q5:S, Q7:D, C_B:P1, U5:VSSA, C_BOOT3:P2, R_BLEED_B1:P1, R_GS5:P2, DZ_G5:A, C_SNUB5:P2, R_SNUB7:P1 to ^CAP_B_POS

Connected Q6:D, Q8:S, C_B:P2, U6:VSSB, R_BLEED_B2:P2, R_GS8:P2, DZ_G8:A, C_SNUB8:P2, R_SNUB6:P1 to ^CAP_B_NEG

Connected Q3:S, Q7:S, U4:VSSA, U6:VSSA, U7:IP+, U7:IP+, C_BOOT2:P2, C_BOOT4:P2, R_GS3:P2, DZ_G3:A, R_GS7:P2, DZ_G7:A, C_SNUB3:P2, C_SNUB7:P2 to ^LOAD_POS

Connected Q4:D, Q8:D, J2:2, R_LOAD_SIM:P2, R_SNUB4:P1, R_SNUB8:P1 to ^LOAD_NEG

Connected U7:IP-, U7:IP-, J2:1, R_LOAD_SIM:P1 to ^LOAD_POS_SENSOR_OUT

Disconnected J1:1, D_TVS_HV:C, R_PRECHG:P1, Q1:D, Q5:D, R_SNUB1:P1, R_SNUB5:P1, J1:2, D_TVS_HV:A, U3:VSSB, U5:VSSB, Q2:S, Q6:S, R_GS2:P2, DZ_G2:A, R_GS6:P2, DZ_G6:A, C_SNUB2:P2, C_SNUB6:P2, Q1:S, Q3:D, C_A:P1, U3:VSSA, C_BOOT1:P2, R_BLEED_A1:P1, R_PRECHG:P2, R_GS1:P2, DZ_G1:A, R_GS3:P2, DZ_G3:A, C_SNUB1:P2, R_SNUB3:P1, Q2:D, Q4:S, C_A:P2, U4:VSSB, R_BLEED_A2:P2, R_GS4:P2, DZ_G4:A, C_SNUB4:P2, R_SNUB2:P1, Q5:S, Q7:D, C_B:P1, U5:VSSA, C_BOOT3:P2, R_BLEED_B1:P1, R_GS5:P2, DZ_G5:A, C_SNUB5:P2, R_SNUB7:P1, Q6:D, Q8:S, C_B:P2, U6:VSSB, R_BLEED_B2:P2, R_GS8:P2, DZ_G8:A, C_SNUB8:P2, R_SNUB6:P1, Q3:S, Q7:S, U4:VSSA, U6:VSSA, U7:IP+, U7:IP+, C_BOOT2:P2, C_BOOT4:P2, Q4:D, Q8:D, J2:2, R_LOAD_SIM:P2, R_SNUB4:P1, R_SNUB8:P1, U7:IP-, U7:IP-, J2:1, R_LOAD_SIM:P1

Added 11 components

6:52

Added 9x Generic Capacitor as C_U3_VCCI, C_U4_VCCI, C_U5_VCCI, C_U6_VCCI, C_U3_VDDB, C_U5_VDDB, C_3V3_BULK, C_15V_BULK, C_NRST (Pins: P1, P2)

Added 2x Generic Resistor as R_BOOT0_PD, R_NRST_PU (Pins: P2, P1)

⚠️ Newly added components are not automatically placed on the PCB layout. If the project has a PCB layout, use `@rewriteLayoutComponentPlacement` to place them on the board.

Connected ^3V3_LOGIC, ^GND_LOGIC, ^GND_LOGIC, and 1 more

5:47

Connected C_U3_VCCI:P1, U3:VCCI, U3:VCCI, C_U4_VCCI:P1, U4:VCCI, U4:VCCI, C_U5_VCCI:P1, U5:VCCI, U5:VCCI to ^3V3_LOGIC

Connected C_U3_VCCI:P2, U3:GND, C_U4_VCCI:P2, U4:GND to ^GND_LOGIC

Connected C_U5_VCCI:P2, U5:GND, C_U6_VCCI:P2, U6:GND, C_3V3_BULK:P2 to ^GND_LOGIC

Connected C_U6_VCCI:P1, U6:VCCI, U6:VCCI, C_3V3_BULK:P1 to ^3V3_LOGIC

Connected ^Net 21, ^Net 22, ^VDD_15V_ISO, and 6 more

5:30

Connected C_U3_VDDB:P1, U3:VDDB to ^Net 21

Connected C_U5_VDDB:P1, U5:VDDB to ^Net 22

Connected C_15V_BULK:P1 to ^VDD_15V_ISO

Connected C_15V_BULK:P2 to ^VSS_ISO

Connected R_BOOT0_PD:P1, U1:PB8-BOOT0 to ^Net 23

Connected R_BOOT0_PD:P2 to ^GND_LOGIC

Connected R_NRST_PU:P1, U1:PG10-NRST, C_NRST:P1 to ^Net 24

Connected R_NRST_PU:P2 to ^3V3_LOGIC

Connected C_NRST:P2 to ^GND_LOGIC

Connected ^GND_PWR

5:09

Connected C_U3_VDDB:P2, U3:VSSB, C_U5_VDDB:P2, U5:VSSB to ^GND_PWR

Placed components

4:38

Placed 14 component(s): C_BOOT2, C_U3_VDDB, C_NRST, C_BOOT1, C_U5_VCCI, C_U4_VCCI, C_U3_VCCI, C_BOOT3, R_BOOT0_PD, R_NRST_PU, C_U6_VCCI, C_U5_VDDB, C_15V_BULK, C_3V3_BULK

Finished working

Q6 D - Q8 S

U3 VDDB - U4 VDDB

D2 C - U4 VDDA

U1 VSS - U1 VSS

D2 C - U4 VDDA

U7 VCC - U1 VDD

D1 C - U3 VDDA

SENSOR_ADC_IN

U3 VDDB - U4 VDDB

D1 C - U3 VDDA

Q2 D - Q4 S

C_B

Capacitance

470uF

C_A

Capacitance

470uF

Not Recommended for New Designs

Reviews

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Project Name

Description

400V 8kW high-speed switched-capacitor energy transfer system with STM32 control, isolated gate drivers, SiC MOSFET matrix, current sensing, 4-layer PCB constraints, and transient simulation intent.

Properties

Implemen… Details

Pricing & Availability

Distributor	Qty 1
Arrow	$136.88–$197.62
Digi-Key	$190.96–$191.59
HQonline	$4.80–$4.88
LCSC	$129.09–$178.68
Mouser	$53.53–$54.29
TME	$201.85
Verical	$65.52–$164.15

Controls

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