High-Speed Energy Transfer System Design
Thought for 5 mins 47 sec
- Connected C_U3_VCCI:P1, U3:VCCI, U3:VCCI, C_U4_VCCI:P1, U4:VCCI, U4:VCCI, C_U5_VCCI:P1, U5:VCCI, U5:VCCI to ^3V3_LOGIC
- Connected C_U3_VCCI:P2, U3:GND, C_U4_VCCI:P2, U4:GND to ^GND_LOGIC
- Connected C_U5_VCCI:P2, U5:GND, C_U6_VCCI:P2, U6:GND, C_3V3_BULK:P2 to ^GND_LOGIC
- Connected C_U6_VCCI:P1, U6:VCCI, U6:VCCI, C_3V3_BULK:P1 to ^3V3_LOGIC
Thought for 5 mins 30 sec
- Connected C_U3_VDDB:P1, U3:VDDB to ^Net 21
- Connected C_U5_VDDB:P1, U5:VDDB to ^Net 22
- Connected C_15V_BULK:P1 to ^VDD_15V_ISO
- Connected C_15V_BULK:P2 to ^VSS_ISO
- Connected R_BOOT0_PD:P1, U1:PB8-BOOT0 to ^Net 23
- Connected R_BOOT0_PD:P2 to ^GND_LOGIC
- Connected R_NRST_PU:P1, U1:PG10-NRST, C_NRST:P1 to ^Net 24
- Connected R_NRST_PU:P2 to ^3V3_LOGIC
- Connected C_NRST:P2 to ^GND_LOGIC
Thought for 5 mins 9 sec
- Connected C_U3_VDDB:P2, U3:VSSB, C_U5_VDDB:P2, U5:VSSB to ^GND_PWR
Thought for 4 mins 38 sec
Placed 14 component(s): C_BOOT2, C_U3_VDDB, C_NRST, C_BOOT1, C_U5_VCCI, C_U4_VCCI, C_U3_VCCI, C_BOOT3, R_BOOT0_PD, R_NRST_PU, C_U6_VCCI, C_U5_VDDB, C_15V_BULK, C_3V3_BULK
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Project Specification
Objective
Build a complete Flux schematic and 4-layer PCB layout for a 400V, 8kW high-speed switched-capacitor energy transfer system.
Required simulation intent
Transient analysis command:
.tran 0 10m 0 10nRequired high-voltage PCB constraint
Maintain at least a 4.0 mm physical gap between GND_LOGIC copper and 400V/high-power nets: VBUS_400V, GND_PWR, CAP_A_POS, CAP_A_NEG, CAP_B_POS, CAP_B_NEG, LOAD_POS, LOAD_NEG.
Required BOM / RefDes
- U1 STM32G474RET6, LQFP-64
- U2 MEJ2D1215SC isolated DC-DC SIP; if unavailable in library, closest physical Murata MEJ2-series SIP part is used and marked for replacement/verification.
- U3-U6 UCC21520DW isolated gate drivers
- U7 ACS730KLCTR-40AB current sensor
- Q1-Q8 C3M0065090D SiC MOSFETs, TO-247-3
- C_A, C_B 470uF 450V capacitor banks, target MPN TDK B43508A5477M
- D1-D4 ES1J bootstrap diodes
- C_BOOT1-C_BOOT4 1uF 50V ceramic bootstrap capacitors
- R_G1-R_G8 2.2 ohm gate resistors
- C_DEC1-C_DEC4 0.1uF ceramic decoupling capacitors
- J1-J2 2-pin high-voltage terminal blocks
Netlist source
The authoritative netlist is the line-by-line netlist provided in the chat execution brief. Connections are implemented explicitly by named nets.
Objective
Required simulation intent
Required high-voltage PCB constraint
Required BOM / RefDes
Netlist source
