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#Goal

- Finalize an ERC‐clean schematic for the MT‑SCT‑2025 board by correcting power/ground connections pin‑by‑pin, ensuring separation of the isolated ADS114S08 domain, wiring RS‑485, Ethernet (with PHY, magnetics, and RJ45), and AI/DI interfaces, and cleaning up the SoC↔DDR3L/eMMC connections. Additionally, prune duplicates while documenting all changes to reach an ERC=0 state.

#Implementation plan

1. **Power/Ground Normalization and Corrections**

1. Reassign and verify power nets (VIN24_IN, VIN24, V5, V3V3_DIG, and ISO_3V3) across the schematic.

2. Perform a pin‑by‑pin review and correction of power and ground connections for the SoC, DDR3L, eMMC, PHY, and buck regulators.

3. Remove stray portals and duplicate connections (retain the lowest‑index instance) and document these changes.

2. **Isolated ADS114S08 Domain Completion**

1. Route U5/U6 (ADS114S08 channel components) onto the ISO_3V3 rail and ensure that all associated grounds and EPs point to GND2 (isolated ground).

2. Implement an isolation band (≥8 mm clearance) between the isolated and main domains, explicitly marking it in the design.

3. Document all modifications in the schematic changes log.

3. **Interface Wiring**

1. RS‑485: Wire the two RS‑485 channels ensuring correct signal routing and termination.

2. Ethernet: Connect the DP83848 PHY to the magnetics (using part JK0654219) and route them through the RJ45 port with added protection (TVS/CMC).

3. AI/DI: Connect the 2 AI inputs and 6 DI channels, verifying logic level appropriateness.

4. SoC↔DDR3L/eMMC: Connect clock, reset, and data lines between the SoC, DDR3L (W632GU6NB‑15), and eMMC (KLM8G1GETF‑B041), following proper grouping and decoupling strategies.

5. Document interface wiring changes.

4. **ERC Run and Documentation Update**

1. Re-run ERC analysis and address any remaining issues until reaching ERC=0.

2. Update the schematic change log with detailed documentation of each corrected net and wiring modification.

3. Export the initial BOM with revised part mappings.

#Success criteria

- All power and ground nets are correctly assigned pin‑by‑pin with no stray connections and with duplicates pruned.

- The isolated ADS114S08 domain is fully compliant with the ≥8 mm isolation band and correctly tied to ISO_3V3/GND2.

- RS‑485, Ethernet, AI/DI, and SoC↔DDR3L/eMMC interfaces are completely wired and functional as per ERC checks.

- The ERC report shows 0 errors and full documentation of changes is complete.

Connected U1:DDR_VDDQCK, U1:DDR_VDDQ, U1:DDR_VDDPLL, U1:DDRPLL_AVDD, U1:IVDD, U1:GIVDD, U1:GEMGXLPLL_AVDD, U1:COREPLL_AVDD, U1:VDD, U3:VCC, U3:VCCQ, U3:VDDI, U2:VREFCA, U2:VDDQ, U2:VDD, U2:VREFDQ, IC3:AVDD33, IC3:IOVDD33, IC1:VOUT, IC2:OUTPUT, IC2:VOUT, IC1:OUTPUT, U9:VCCA, U10:VCCA, U21:VCCA, U22:VCCA, U33:VCCA, U34:VCCA to ^V3V3_DIG

Connected L1:2 to ^VIN24 2

Connected F4:P2, U4:VIN, U4:~ON~/OFF, D10:~, D9:K to ^VIN24

Connected F4:P1 to ^VIN24_IN 2

Disconnected U1:DDR_VDDQCK, U1:DDR_VDDQ, U1:DDR_VDDPLL, U1:DDRPLL_AVDD, U1:IVDD, U1:GIVDD, U1:GEMGXLPLL_AVDD, U1:COREPLL_AVDD, U1:VDD, U2:VREFCA, U2:VDDQ, U2:VDD, U2:VREFDQ, U3:VCC, U3:VCCQ, U3:VDDI, IC3:AVDD33, IC3:IOVDD33, IC1:VOUT, IC1:OUTPUT, IC2:OUTPUT, IC2:VOUT, U9:VCCA, U10:VCCA, U21:VCCA, U22:VCCA, U33:VCCA, U34:VCCA, L1:2, F4:P2, U4:VIN, U4:~ON~/OFF, D10:~, D9:K, F4:P1

nets {

net GND2 = U35:VEE, U22:GNDB, U23:VEE, U11:VEE, U6:AVSS-SW, U6:AVSS, U6:DGND, U5:AVSS-SW, U5:AVSS, U5:DGND, U9:GNDB, U12:VEE, U10:GNDB, U34:GNDB, U24:VEE, U33:GNDB, U21:GNDB, U36:VEE;

net ISO_3V3 = U34:VCCB, U24:VCC1, U21:VCCB, U33:VCCB, U5:IOVDD, U5:DVDD, U6:IOVDD, U6:DVDD, U5:AVDD, U12:VCC1, U23:VCC1, U22:VCCB, U9:VCCB, U6:AVDD, U35:VCC1, U10:VCCB, IC6:VOUT, IC7:OUTPUT, IC6:OUTPUT, IC12:VOUT, IC7:VOUT, IC11:VOUT, IC12:OUTPUT, IC11:OUTPUT, U36:VCC1, U11:VCC1;

net GND1 2 = U2:VDD, U2:VREFDQ, IC3:AVDD33, IC3:IOVDD33, U34:VCCA, U33:VCCA, U22:VCCA, U21:VCCA, U10:VCCA, U9:VCCA, IC1:OUTPUT, IC2:VOUT, IC2:OUTPUT, IC1:VOUT, U2:VDDQ, U2:VREFCA, U3:VDDI, U3:VCCQ, U3:VCC, U1:VDD, U1:COREPLL_AVDD, U1:GEMGXLPLL_AVDD, U1:GIVDD, U1:IVDD, U1:DDRPLL_AVDD, U1:DDR_VDDPLL, U1:DDR_VDDQ, U1:DDR_VDDQCK;

net GND1 2 = IC7:ADJ/GND, IC3:IOGND, IC3:DGND, IC3:AGND, U2:VSS, U1:IVSS, IC11:ADJ/GND, D9:A, U4:GND_TAB, U4:GROUND, U34:GNDA, U10:GNDA, U9:GNDA, U33:GNDA, U21:GNDA, U22:GNDA, U1:VSS, U1:DDRPLL_AVSS, U2:VSSQ, U1:GIVSS, L1:1, IC12:ADJ/GND, U1:GEMGXLPLL_AVSS, IC1:ADJ/GND, U1:COREPLL_AVSS, U3:VSS, IC6:ADJ/GND, IC2:ADJ/GND;

net Net 7 = U1:IVDD, U1:VDD;

net V5 = U4:OUTPUT, U4:FEEDBACK, IC12:INPUT, IC2:INPUT, IC7:INPUT, IC6:INPUT, IC1:INPUT, IC11:INPUT;

net Net 8 = U1:DDR_VDDQ, U1:DDR_VDDPLL;

net VIN24 2 = L1:2;

net VIN24 = F4:P2, U4:VIN, U4:~ON~/OFF, D9:K, D10:~;

net VIN24_IN 2 = F4:P1;

}