ESP32-S3 System Design Inquiry

2:46

General
Chat History
Project
Knowledge Base
Schematic

Using Knowledge Base Tool.

Using Schematic Tool.

You’re right. Many of the decoupling capacitors I added as placeholders were never wired. Here’s the current state and how I’ll fix it.
What’s unconnected now
  • Unconnected caps: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12.
  • Connected rail caps (ok): SYS bulk/decoupling C13, C14; 3.3 V bulk/decoupling C15, C16.
  • Relevant ICs and rails: charger U1 (SYS), buck‑boost U2 (3.3 V), fuel gauge U3, MCU U4, camera U5, display U6, test points TP1/TP2/TP3/TP4, Tag‑Connect J4, duplicate Tag‑Connect J5.
Why this happened
  • I placed a decoupling/bulk “budget” up front and only tied the main rail caps. The per‑IC local 100 nF caps were not yet wired to each IC’s power pin/GND.
Recommended decoupling cleanup (concise and cost‑effective)
  • Keep rail decoupling as placed:
    • SYS (U1 OUT): [C13] 100 nF + [C14] 10 µF to GND.
    • 3.3 V (U2 VOUT): [C15] 100 nF + [C16] 10 µF to GND.
  • Add one local 100 nF at each powered IC and module:
    • [U4] ESP32 3.3 V: wire one of [C7]/[C8] to 3.3 V and GND near VDD3P3 pins.
    • [U5] OV2640 3.3 V: wire one of [C9]/[C10] to 3.3 V and GND near pin 1.
    • [U6] ST7789 3.3 V: wire one of [C11]/[C12] to 3.3 V and GND near 3V.
    • [U3] MAX17055: wire one of [C5]/[C6] (100 nF) from its 3.3 V pin to GND.
  • Remove the rest of the unused capacitors to avoid clutter and confusion.
Notes from best practices I’ll follow
  • Use a typical combo of 100 nF + 1 µF + 10 µF to cover high and low frequencies where needed, prioritizing the 100 nF right at the IC pin, with larger values nearby.
  • Ensure capacitor voltage ratings run at no more than 60% of their maximum rated voltage.
Want me to fix it now?
  • I can wire: C7/C8→[U4] 3.3 V, C9/C10→[U5] 3.3 V, C11/C12→[U6] 3.3 V, C5/C6→[U3] 3.3 V; keep [C13]–[C16] as rail decoupling; delete the extra unused caps; and also remove the duplicate Tag‑Connect J5.
  • Confirm and I’ll apply these connections and cleanups in one pass.
112 days
U2 is not fully connected too, hmmm....
112 days

2:24

General
Chat History
Project
Knowledge Base
Plan
U2

Using Knowledge Base Tool.

You’re right: U2 isn’t fully wired. I’ve prepared a fix plan to complete it and correct the power nets.
Planned changes:
  • Correct SYS path: keep U7:BAT→U1:IN only; isolate U1:OUT as SYS feeding U2:VIN.
  • Finish U2: add inductor between its switch pins, FB divider for 3.3 V, tie EN to SYS, set PS/SYNC, add PG pull-up, complete AGND/PGND, and place 100 nF + 10 µF on VIN and VOUT.
  • Reconnect 3.3 V from U2:VOUT to all loads: U4, U5, U6, U3, and test points.
  • Decoupling cleanup: keep rail bulk caps, add one 100 nF local at each IC, remove stray unused caps. Then run ERC.
Click Start on the plan bar and I’ll execute these fixes.
112 days

Started implementing a plan

#Goal

- Fully connect the TPS63020 (U2) buck-boost converter and correct the surrounding power paths to ensure that the 3.3V rail is valid, stable, and reliable for all connected loads in the ESP32-S3-PICO-N2R8 Qi-powered camera system.

#Implementation plan

1. Correct Power Path Nets

1. Disconnect SYS from U1:IN and keep U7:BAT feeding only U1:IN.

2. Isolate U1:OUT as the SYS rail and verify that it exclusively feeds U2:VIN.

2. Fully Connect U2 (TPS63020) per the Datasheet

1. Add the inductor between the appropriate pins (L1/L2) as recommended.

2. Implement the feedback (FB) divider circuit to generate the 3.3V output from U2:VOUT.

3. Tie U2:EN to the SYS rail with an appropriate pull-up resistor.

4. Configure the PS/SYNC and PG pins of U2: ensure a pull-up is added on PG.

5. Connect AGND and PGND appropriately.

6. Place decoupling capacitors (100 nF and 10 µF) at VIN and VOUT for proper regulation and noise suppression; also ensure any additional VINA decoupling per datasheet guidance.

3. Distribute the 3.3V Rail

1. Connect U2:VOUT to the rest of the loads including U4 (ESP32-PICO-D4), U5 (OV2640), U6 (Adafruit ST7789 TFT), U3 (MAX17055), pull-ups, and test points.

4. Clean Decoupling and Unused Components

1. Place a local 100 nF capacitor at each critical IC (ESP32, OV2640, ST7789, MAX17055).

2. Retain the bulk rail decoupling capacitors as needed and remove any stray or unused capacitors (C1–C12) that are not correctly connected.

5. Final ERC and Schematic Verification

1. Review the schematic ensuring all non-connected pins on U2 and other ICs are correctly connected.

2. Run ERC to confirm that there are no errors and that the complete power network is compliant with design guidelines.

#Success criteria

- The TPS63020 (U2) is fully connected per its datasheet recommendations including proper inductor, FB divider, EN, PG, and PS/SYNC connections with appropriate decoupling.

- The power path is corrected so that the SYS rail (U1:OUT) exclusively feeds U2:VIN and supplies 3.3V to U4, U5, U6, U3, and associated test points, with no accidental ties to U1:IN.

- The decoupling scheme is optimal with local caps at each IC and no stray unused components.

- Electrical Rule Check (ERC) passes with no errors related to U2 and power nets.

112 days

Started implementing a plan

#Goal

- Fully connect the TPS63020 (U2) buck-boost converter and correct the surrounding power paths to ensure that the 3.3V rail is valid, stable, and reliable for all connected loads in the ESP32-S3-PICO-N2R8 Qi-powered camera system.

#Implementation plan

1. Correct Power Path Nets

1. Disconnect SYS from U1:IN and keep U7:BAT feeding only U1:IN.

2. Isolate U1:OUT as the SYS rail and verify that it exclusively feeds U2:VIN.

2. Fully Connect U2 (TPS63020) per the Datasheet

1. Add the inductor between the appropriate pins (L1/L2) as recommended.

2. Implement the feedback (FB) divider circuit to generate the 3.3V output from U2:VOUT.

3. Tie U2:EN to the SYS rail with an appropriate pull-up resistor.

4. Configure the PS/SYNC and PG pins of U2: ensure a pull-up is added on PG.

5. Connect AGND and PGND appropriately.

6. Place decoupling capacitors (100 nF and 10 µF) at VIN and VOUT for proper regulation and noise suppression; also ensure any additional VINA decoupling per datasheet guidance.

3. Distribute the 3.3V Rail

1. Connect U2:VOUT to the rest of the loads including U4 (ESP32-PICO-D4), U5 (OV2640), U6 (Adafruit ST7789 TFT), U3 (MAX17055), pull-ups, and test points.

4. Clean Decoupling and Unused Components

1. Place a local 100 nF capacitor at each critical IC (ESP32, OV2640, ST7789, MAX17055).

2. Retain the bulk rail decoupling capacitors as needed and remove any stray or unused capacitors (C1–C12) that are not correctly connected.

5. Final ERC and Schematic Verification

1. Review the schematic ensuring all non-connected pins on U2 and other ICs are correctly connected.

2. Run ERC to confirm that there are no errors and that the complete power network is compliant with design guidelines.

#Success criteria

- The TPS63020 (U2) is fully connected per its datasheet recommendations including proper inductor, FB divider, EN, PG, and PS/SYNC connections with appropriate decoupling.

- The power path is corrected so that the SYS rail (U1:OUT) exclusively feeds U2:VIN and supplies 3.3V to U4, U5, U6, U3, and associated test points, with no accidental ties to U1:IN.

- The decoupling scheme is optimal with local caps at each IC and no stray unused components.

- Electrical Rule Check (ERC) passes with no errors related to U2 and power nets.

112 days

Working...

Show Plan


U6
J1 PIN1 - U1 BAT
U2 VOS - U5 3.3V
U4 IO16 - U5 HREF
U4 IO25 - U5 D6
U1 VSS - U2 AGND
U4 IO19 - U5 D2
U4 IO17 - U6 RST
U4 IO21 - U5 D3
U4 IO13 - U5 SIOC
U1 VSS - U2 AGND
U4 IO22 - U5 D4
U4 IO26 - U5 D7
U4 IO12 - U5 SIOD
U4 IO16 - U5 HREF
U4 IO14 - U5 PCLK
U4 IO4 - U5 XCLK
U4 IO19 - U5 D2
U4 IO22 - U5 D4
U2 VOS - U5 3.3V
U4 IO23 - U5 D5
U2 VOS - U5 3.3V
U4 IO23 - U5 D5
U4 IO27 - U5 D8
U1 VSS - U2 AGND
U4 IO15 - U5 VSYNK
U4 IO12 - U5 SIOD
U2 VOS - U5 3.3V
U1 VSS - U2 AGND
U4 IO32 - U5 D9
U4 IO13 - U5 SIOC
U4 IO18 - U6 SCK
U1 VSS - U2 AGND
U4 IO5 - U6 TFTCS
U1 VSS - U2 AGND
U4 IO21 - U5 D3
U5
U4
End of Life
TP4
TP1
U1
TP2
TP3


  • Ground
    A common return path for electric current. Commonly known as ground.
  • Net Portal
    Wirelessly connects nets on schematic. Used to organize schematics and separate functional blocks. To wirelessly connect net portals, give them same designator. #portal
  • Power Net Portal
    Wirelessly connects power nets on schematic. Identical to the net portal, but with a power symbol. Used to organize schematics and separate functional blocks. To wirelessly connect power net portals, give them the same designator. #portal #power
  • Generic Resistor
    A generic fixed resistor for rapid developing circuit topology. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard resistor values: 1.0Ω 10Ω 100Ω 1.0kΩ 10kΩ 100kΩ 1.0MΩ 1.1Ω 11Ω 110Ω 1.1kΩ 11kΩ 110kΩ 1.1MΩ 1.2Ω 12Ω 120Ω 1.2kΩ 12kΩ 120kΩ 1.2MΩ 1.3Ω 13Ω 130Ω 1.3kΩ 13kΩ 130kΩ 1.3MΩ 1.5Ω 15Ω 150Ω 1.5kΩ 15kΩ 150kΩ 1.5MΩ 1.6Ω 16Ω 160Ω 1.6kΩ 16kΩ 160kΩ 1.6MΩ 1.8Ω 18Ω 180Ω 1.8KΩ 18kΩ 180kΩ 1.8MΩ 2.0Ω 20Ω 200Ω 2.0kΩ 20kΩ 200kΩ 2.0MΩ 2.2Ω 22Ω 220Ω 2.2kΩ 22kΩ 220kΩ 2.2MΩ 2.4Ω 24Ω 240Ω 2.4kΩ 24kΩ 240kΩ 2.4MΩ 2.7Ω 27Ω 270Ω 2.7kΩ 27kΩ 270kΩ 2.7MΩ 3.0Ω 30Ω 300Ω 3.0KΩ 30KΩ 300KΩ 3.0MΩ 3.3Ω 33Ω 330Ω 3.3kΩ 33kΩ 330kΩ 3.3MΩ 3.6Ω 36Ω 360Ω 3.6kΩ 36kΩ 360kΩ 3.6MΩ 3.9Ω 39Ω 390Ω 3.9kΩ 39kΩ 390kΩ 3.9MΩ 4.3Ω 43Ω 430Ω 4.3kΩ 43KΩ 430KΩ 4.3MΩ 4.7Ω 47Ω 470Ω 4.7kΩ 47kΩ 470kΩ 4.7MΩ 5.1Ω 51Ω 510Ω 5.1kΩ 51kΩ 510kΩ 5.1MΩ 5.6Ω 56Ω 560Ω 5.6kΩ 56kΩ 560kΩ 5.6MΩ 6.2Ω 62Ω 620Ω 6.2kΩ 62KΩ 620KΩ 6.2MΩ 6.8Ω 68Ω 680Ω 6.8kΩ 68kΩ 680kΩ 6.8MΩ 7.5Ω 75Ω 750Ω 7.5kΩ 75kΩ 750kΩ 7.5MΩ 8.2Ω 82Ω 820Ω 8.2kΩ 82kΩ 820kΩ 8.2MΩ 9.1Ω 91Ω 910Ω 9.1kΩ 91kΩ 910kΩ 9.1MΩ #generics #CommonPartsLibrary
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    A generic fixed capacitor ideal for rapid circuit topology development. You can choose between polarized and non-polarized types, its symbol and the footprint will automatically adapt based on your selection. Supported options include standard SMD sizes for ceramic capacitors (e.g., 0402, 0603, 0805), SMD sizes for aluminum electrolytic capacitors, and through-hole footprints for polarized capacitors. Save precious design time by seamlessly add more information to this part (value, footprint, etc.) as it becomes available. Standard capacitor values: 1.0pF 10pF 100pF 1000pF 0.01uF 0.1uF 1.0uF 10uF 100uF 1000uF 10,000uF 1.1pF 11pF 110pF 1100pF 1.2pF 12pF 120pF 1200pF 1.3pF 13pF 130pF 1300pF 1.5pF 15pF 150pF 1500pF 0.015uF 0.15uF 1.5uF 15uF 150uF 1500uF 1.6pF 16pF 160pF 1600pF 1.8pF 18pF 180pF 1800pF 2.0pF 20pF 200pF 2000pF 2.2pF 22pF 20pF 2200pF 0.022uF 0.22uF 2.2uF 22uF 220uF 2200uF 2.4pF 24pF 240pF 2400pF 2.7pF 27pF 270pF 2700pF 3.0pF 30pF 300pF 3000pF 3.3pF 33pF 330pF 3300pF 0.033uF 0.33uF 3.3uF 33uF 330uF 3300uF 3.6pF 36pF 360pF 3600pF 3.9pF 39pF 390pF 3900pF 4.3pF 43pF 430pF 4300pF 4.7pF 47pF 470pF 4700pF 0.047uF 0.47uF 4.7uF 47uF 470uF 4700uF 5.1pF 51pF 510pF 5100pF 5.6pF 56pF 560pF 5600pF 6.2pF 62pF 620pF 6200pF 6.8pF 68pF 680pF 6800pF 0.068uF 0.68uF 6.8uF 68uF 680uF 6800uF 7.5pF 75pF 750pF 7500pF 8.2pF 82pF 820pF 8200pF 9.1pF 91pF 910pF 9100pF #generics #CommonPartsLibrary
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  • Terminal
    Terminal
    An electrical connector acting as reusable interface to a conductor and creating a point where external circuits can be connected.
  • RMCF0805JT47K0
    47 kOhms ±5% 0.125W, 1/8W Chip Resistor 0805 (2012 Metric) Automotive AEC-Q200 Thick Film #forLedBlink
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    10uF Capacitor Aluminum Polymer 20% 16V SMD 5x5.3mm #forLedBlink #commonpartslibrary #capacitor #aluminumpolymer #radialcan
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    Yellow 595nm LED Indication - Discrete 1.7V 1206 (3216 Metric) #forLedBlink

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